From 08bf21e4b04621152ae91c3ac622030a4fa8764c Mon Sep 17 00:00:00 2001
From: Samuel Holland <samuel@sholland.org>
Date: Sat, 6 Aug 2022 00:46:21 -0500
Subject: [PATCH 58/68] riscv: Add CONFIG_TARGET_SUN20I

This target is used for Allwinner's sun20i series of RISC-V SoCs,
starting with the Allwinner D1 and D1s.

Signed-off-by: Samuel Holland <samuel@sholland.org>
---
 arch/riscv/Kconfig            |  9 +++++++++
 board/sunxi/Kconfig           | 24 +++++++++++++++++++++++-
 common/spl/Kconfig            |  1 +
 drivers/clk/sunxi/Kconfig     |  2 +-
 drivers/pinctrl/sunxi/Kconfig | 10 +++++-----
 include/configs/sun20i.h      | 11 +++++++++++
 6 files changed, 50 insertions(+), 7 deletions(-)
 create mode 100644 include/configs/sun20i.h

--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -31,6 +31,15 @@ config TARGET_SIPEED_MAIX
 	bool "Support Sipeed Maix Board"
 	select SYS_CACHE_SHIFT_6
 
+config TARGET_SUN20I_D1
+	bool "Support Allwinner D1 Boards"
+	select BOARD_SUNXI
+	select GENERIC_RISCV
+	select MMC_SUNXI_HAS_NEW_MODE
+	select SUNXI_GEN_NCAT2
+	select SUNXI_NEW_PINCTRL
+	select THEAD_C906
+
 config TARGET_STARFIVE_VISIONFIVE2
 	bool "Support StarFive VisionFive2 Board"
 	select BOARD_LATE_INIT
--- a/board/sunxi/Kconfig
+++ b/board/sunxi/Kconfig
@@ -14,6 +14,15 @@ config BOARD_SUNXI
 	select DM_SPI_FLASH if SPI
 	select OF_BOARD_SETUP
 	select PINCTRL
+	select RAM if SPL_DM
+	select SPL_CLK if SPL_DM
+	select SPL_DM if RISCV && SPL
+	select SPL_DM_SPI if SPL_DM && SPL_SPI
+	select SPL_DM_SPI_FLASH if SPL_DM && SPL_SPI
+	select SPL_OF_CONTROL if SPL_DM
+	select SPL_PINCTRL if SPL_DM
+	select SPL_PINCONF if SPL_DM
+	select SPL_RAM if SPL_DM
 	select SPL_SEPARATE_BSS if SPL
 	select SUPPORT_SPL
 	select SYS_RELOC_GD_ENV_ADDR
@@ -29,6 +38,7 @@ config BOARD_SUNXI
 	imply DM_REGULATOR_FIXED
 	imply FAT_WRITE
 	imply FIT
+	imply MMC
 	imply OF_LIBFDT_OVERLAY
 	imply PRE_CONSOLE_BUFFER
 	imply SPL
@@ -43,6 +53,7 @@ config BOARD_SUNXI
 	imply SYS_I2C_MVTWSI
 	imply SYS_NS16550
 	imply SYSRESET
+	imply SYSRESET_SBI
 	imply SYSRESET_WATCHDOG
 	imply SYSRESET_WATCHDOG_AUTO
 	imply USB_EHCI_GENERIC
@@ -69,6 +80,12 @@ config SPL_BSS_START_ADDR
 	default 0x4ff80000 if SUNXI_MINIMUM_DRAM_MB >= 256
 	default 0x43f80000 if SUNXI_MINIMUM_DRAM_MB >= 64
 
+config SPL_OPENSBI_LOAD_ADDR
+	default 0x40000000 if RISCV
+
+config SPL_STACK
+	default 0x48000 if TARGET_SUN20I_D1
+
 config SPL_STACK_R_ADDR
 	default 0x81e00000 if MACH_SUNIV
 	default 0x2fe00000 if MACH_SUN9I
@@ -89,7 +106,7 @@ config SUNXI_GEN_NCAT2
 config SUNXI_MINIMUM_DRAM_MB
 	int
 	default 32 if MACH_SUNIV
-	default 64 if MACH_SUN8I_V3S
+	default 64 if MACH_SUN8I_V3S || TARGET_SUN20I_D1
 	default 256
 	help
 	  Minimum DRAM size expected on the board. Traditionally we
@@ -122,6 +139,7 @@ config SYS_CLK_FREQ
 	default 1008000000 if MACH_SUN8I
 	default 1008000000 if MACH_SUN8I_R528
 	default 1008000000 if MACH_SUN9I
+	default 1008000000 if TARGET_SUN20I_D1
 	default  816000000 if MACH_SUN50I || MACH_SUN50I_H5
 	default  888000000 if MACH_SUN50I_H6
 	default 1008000000 if MACH_SUN50I_H616
@@ -135,10 +153,14 @@ config SYS_CONFIG_NAME
 	default "sun8i"  if MACH_SUN8I
 	default "sun8i"  if MACH_SUN8I_R528
 	default "sun9i"  if MACH_SUN9I
+	default "sun20i" if TARGET_SUN20I_D1
 	default "sun50i" if MACH_SUN50I
 	default "sun50i" if MACH_SUN50I_H6
 	default "sun50i" if MACH_SUN50I_H616
 
+config SYS_CPU
+	default "thead" if TARGET_SUN20I_D1
+
 config SYS_LOAD_ADDR
 	default 0x81000000 if MACH_SUNIV
 	default 0x22000000 if MACH_SUN9I
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -77,6 +77,7 @@ config SPL_SIZE_LIMIT_PROVIDE_STACK
 config SPL_MAX_SIZE
 	hex "Maximum size of the SPL image, excluding BSS"
 	default 0x30000 if ARCH_MX6 && MX6_OCRAM_256KB
+	default 0x27fa0 if TARGET_SUN20I_D1
 	default 0x1b000 if AM33XX && !TI_SECURE_DEVICE
 	default 0x10000 if ARCH_MX6 && !MX6_OCRAM_256KB
 	default 0x7fa0 if SUNXI_SRAM_ADDRESS = 0x10000
--- a/drivers/clk/sunxi/Kconfig
+++ b/drivers/clk/sunxi/Kconfig
@@ -89,7 +89,7 @@ config CLK_SUN8I_H3
 
 config CLK_SUN20I_D1
 	bool "Clock driver for Allwinner D1"
-	default MACH_SUN8I_R528
+	default MACH_SUN8I_R528 || TARGET_SUN20I_D1
 	help
 	  This enables common clock driver support for platforms based
 	  on Allwinner D1 SoC.
--- a/drivers/pinctrl/sunxi/Kconfig
+++ b/drivers/pinctrl/sunxi/Kconfig
@@ -89,6 +89,11 @@ config PINCTRL_SUN9I_A80_R
 	default MACH_SUN9I
 	select PINCTRL_SUNXI
 
+config PINCTRL_SUN20I_D1
+	bool "Support for the Allwinner D1/R528 PIO"
+	default MACH_SUN8I_R528 || TARGET_SUN20I_D1
+	select PINCTRL_SUNXI
+
 config PINCTRL_SUN50I_A64
 	bool "Support for the Allwinner A64 PIO"
 	default MACH_SUN50I
@@ -124,9 +129,4 @@ config PINCTRL_SUN50I_H616_R
 	default MACH_SUN50I_H616
 	select PINCTRL_SUNXI
 
-config PINCTRL_SUN20I_D1
-	bool "Support for the Allwinner D1/R528 PIO"
-	default MACH_SUN8I_R528
-	select PINCTRL_SUNXI
-
 endif
--- /dev/null
+++ b/include/configs/sun20i.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Placeholder wrapper to allow addressing Allwinner D1 (and later) sun20i
+ * CPU based devices separately. Please do not add anything in here.
+ */
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+#include <configs/sunxi-common.h>
+
+#endif /* __CONFIG_H */
