From 8b097eba8b5e48efe73d5298ff2dce11cd9d16cb Mon Sep 17 00:00:00 2001
From: Daniel Machon <daniel.machon@microchip.com>
Date: Thu, 5 Dec 2024 14:54:24 +0100
Subject: [PATCH 65/82] net: lan969x: fix cyclic dependency reported by depmod

Depmod reports a cyclic dependency between modules sparx5-switch.ko and
lan969x-switch.ko:

depmod: ERROR: Cycle detected: lan969x_switch -> sparx5_switch -> lan969x_switch
depmod: ERROR: Found 2 modules in dependency cycles!
make[2]: *** [scripts/Makefile.modinst:132: depmod] Error 1
make: *** [Makefile:224: __sub-make] Error 2

This makes sense, as they both require symbols from each other.

Fix this by compiling lan969x support into the sparx5-switch.ko module.
In order to do this, in a sensible way, we move the lan969x/ dir into
the sparx5/ dir and do some code cleanup of code that is no longer
required.

After this patch, depmod will no longer complain, as lan969x support is
compiled into the sparx5-swicth.ko module, and can no longer be compiled
as a standalone module.

Fixes: 98a01119608d ("net: sparx5: add compatible string for lan969x")
Signed-off-by: Daniel Machon <daniel.machon@microchip.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
---
 MAINTAINERS                                         |  2 +-
 drivers/net/ethernet/microchip/Kconfig              |  1 -
 drivers/net/ethernet/microchip/Makefile             |  1 -
 drivers/net/ethernet/microchip/lan969x/Kconfig      |  5 -----
 drivers/net/ethernet/microchip/lan969x/Makefile     | 13 -------------
 drivers/net/ethernet/microchip/sparx5/Kconfig       |  6 ++++++
 drivers/net/ethernet/microchip/sparx5/Makefile      |  6 ++++++
 .../microchip/{ => sparx5}/lan969x/lan969x.c        |  5 -----
 .../microchip/{ => sparx5}/lan969x/lan969x.h        |  0
 .../{ => sparx5}/lan969x/lan969x_calendar.c         |  0
 .../microchip/{ => sparx5}/lan969x/lan969x_regs.c   |  0
 .../{ => sparx5}/lan969x/lan969x_vcap_ag_api.c      |  0
 .../{ => sparx5}/lan969x/lan969x_vcap_impl.c        |  0
 .../net/ethernet/microchip/sparx5/sparx5_calendar.c |  2 --
 drivers/net/ethernet/microchip/sparx5/sparx5_main.c |  4 ++--
 drivers/net/ethernet/microchip/sparx5/sparx5_ptp.c  |  1 -
 16 files changed, 15 insertions(+), 31 deletions(-)
 delete mode 100644 drivers/net/ethernet/microchip/lan969x/Kconfig
 delete mode 100644 drivers/net/ethernet/microchip/lan969x/Makefile
 rename drivers/net/ethernet/microchip/{ => sparx5}/lan969x/lan969x.c (98%)
 rename drivers/net/ethernet/microchip/{ => sparx5}/lan969x/lan969x.h (100%)
 rename drivers/net/ethernet/microchip/{ => sparx5}/lan969x/lan969x_calendar.c (100%)
 rename drivers/net/ethernet/microchip/{ => sparx5}/lan969x/lan969x_regs.c (100%)
 rename drivers/net/ethernet/microchip/{ => sparx5}/lan969x/lan969x_vcap_ag_api.c (100%)
 rename drivers/net/ethernet/microchip/{ => sparx5}/lan969x/lan969x_vcap_impl.c (100%)

--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -15159,7 +15159,7 @@ M:	Daniel Machon <daniel.machon@microchi
 M:	UNGLinuxDriver@microchip.com
 L:	netdev@vger.kernel.org
 S:	Maintained
-F:	drivers/net/ethernet/microchip/lan969x/*
+F:	drivers/net/ethernet/microchip/sparx5/lan969x/*
 
 MICROCHIP LCDFB DRIVER
 M:	Nicolas Ferre <nicolas.ferre@microchip.com>
--- a/drivers/net/ethernet/microchip/Kconfig
+++ b/drivers/net/ethernet/microchip/Kconfig
@@ -59,7 +59,6 @@ config LAN743X
 
 source "drivers/net/ethernet/microchip/lan865x/Kconfig"
 source "drivers/net/ethernet/microchip/lan966x/Kconfig"
-source "drivers/net/ethernet/microchip/lan969x/Kconfig"
 source "drivers/net/ethernet/microchip/sparx5/Kconfig"
 source "drivers/net/ethernet/microchip/vcap/Kconfig"
 source "drivers/net/ethernet/microchip/fdma/Kconfig"
--- a/drivers/net/ethernet/microchip/Makefile
+++ b/drivers/net/ethernet/microchip/Makefile
@@ -11,7 +11,6 @@ lan743x-objs := lan743x_main.o lan743x_e
 
 obj-$(CONFIG_LAN865X) += lan865x/
 obj-$(CONFIG_LAN966X_SWITCH) += lan966x/
-obj-$(CONFIG_LAN969X_SWITCH) += lan969x/
 obj-$(CONFIG_SPARX5_SWITCH) += sparx5/
 obj-$(CONFIG_VCAP) += vcap/
 obj-$(CONFIG_FDMA) += fdma/
--- a/drivers/net/ethernet/microchip/lan969x/Kconfig
+++ /dev/null
@@ -1,5 +0,0 @@
-config LAN969X_SWITCH
-	bool "Lan969x switch driver"
-	depends on SPARX5_SWITCH
-	help
-	  This driver supports the lan969x family of network switch devices.
--- a/drivers/net/ethernet/microchip/lan969x/Makefile
+++ /dev/null
@@ -1,13 +0,0 @@
-# SPDX-License-Identifier: GPL-2.0-only
-#
-# Makefile for the Microchip lan969x network device drivers.
-#
-
-obj-$(CONFIG_SPARX5_SWITCH) += lan969x-switch.o
-
-lan969x-switch-y := lan969x_regs.o lan969x.o lan969x_calendar.o \
- lan969x_vcap_ag_api.o lan969x_vcap_impl.o
-
-# Provide include files
-ccflags-y += -I$(srctree)/drivers/net/ethernet/microchip/fdma
-ccflags-y += -I$(srctree)/drivers/net/ethernet/microchip/vcap
--- a/drivers/net/ethernet/microchip/sparx5/Kconfig
+++ b/drivers/net/ethernet/microchip/sparx5/Kconfig
@@ -24,3 +24,9 @@ config SPARX5_DCB
 	  DSCP and PCP.
 
 	  If unsure, set to Y.
+
+config LAN969X_SWITCH
+	bool "Lan969x switch driver"
+	depends on SPARX5_SWITCH
+	help
+	  This driver supports the lan969x family of network switch devices.
--- a/drivers/net/ethernet/microchip/sparx5/Makefile
+++ b/drivers/net/ethernet/microchip/sparx5/Makefile
@@ -16,6 +16,12 @@ sparx5-switch-y  := sparx5_main.o sparx5
 sparx5-switch-$(CONFIG_SPARX5_DCB) += sparx5_dcb.o
 sparx5-switch-$(CONFIG_DEBUG_FS) += sparx5_vcap_debugfs.o
 
+sparx5-switch-$(CONFIG_LAN969X_SWITCH) += lan969x/lan969x_regs.o \
+					  lan969x/lan969x.o \
+					  lan969x/lan969x_calendar.o \
+					  lan969x/lan969x_vcap_ag_api.o \
+					  lan969x/lan969x_vcap_impl.o
+
 # Provide include files
 ccflags-y += -I$(srctree)/drivers/net/ethernet/microchip/vcap
 ccflags-y += -I$(srctree)/drivers/net/ethernet/microchip/fdma
--- a/drivers/net/ethernet/microchip/lan969x/lan969x.c
+++ /dev/null
@@ -1,353 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/* Microchip lan969x Switch driver
- *
- * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries.
- */
-
-#include "lan969x.h"
-
-#define LAN969X_SDLB_GRP_CNT 5
-#define LAN969X_HSCH_LEAK_GRP_CNT 4
-
-static const struct sparx5_main_io_resource lan969x_main_iomap[] =  {
-	{ TARGET_CPU,                   0xc0000, 0 }, /* 0xe00c0000 */
-	{ TARGET_FDMA,                  0xc0400, 0 }, /* 0xe00c0400 */
-	{ TARGET_GCB,                 0x2010000, 1 }, /* 0xe2010000 */
-	{ TARGET_QS,                  0x2030000, 1 }, /* 0xe2030000 */
-	{ TARGET_PTP,                 0x2040000, 1 }, /* 0xe2040000 */
-	{ TARGET_ANA_ACL,             0x2050000, 1 }, /* 0xe2050000 */
-	{ TARGET_LRN,                 0x2060000, 1 }, /* 0xe2060000 */
-	{ TARGET_VCAP_SUPER,          0x2080000, 1 }, /* 0xe2080000 */
-	{ TARGET_QSYS,                0x20a0000, 1 }, /* 0xe20a0000 */
-	{ TARGET_QFWD,                0x20b0000, 1 }, /* 0xe20b0000 */
-	{ TARGET_XQS,                 0x20c0000, 1 }, /* 0xe20c0000 */
-	{ TARGET_VCAP_ES2,            0x20d0000, 1 }, /* 0xe20d0000 */
-	{ TARGET_VCAP_ES0,            0x20e0000, 1 }, /* 0xe20e0000 */
-	{ TARGET_ANA_AC_POL,          0x2200000, 1 }, /* 0xe2200000 */
-	{ TARGET_QRES,                0x2280000, 1 }, /* 0xe2280000 */
-	{ TARGET_EACL,                0x22c0000, 1 }, /* 0xe22c0000 */
-	{ TARGET_ANA_CL,              0x2400000, 1 }, /* 0xe2400000 */
-	{ TARGET_ANA_L3,              0x2480000, 1 }, /* 0xe2480000 */
-	{ TARGET_ANA_AC_SDLB,         0x2500000, 1 }, /* 0xe2500000 */
-	{ TARGET_HSCH,                0x2580000, 1 }, /* 0xe2580000 */
-	{ TARGET_REW,                 0x2600000, 1 }, /* 0xe2600000 */
-	{ TARGET_ANA_L2,              0x2800000, 1 }, /* 0xe2800000 */
-	{ TARGET_ANA_AC,              0x2900000, 1 }, /* 0xe2900000 */
-	{ TARGET_VOP,                 0x2a00000, 1 }, /* 0xe2a00000 */
-	{ TARGET_DEV2G5,              0x3004000, 1 }, /* 0xe3004000 */
-	{ TARGET_DEV10G,              0x3008000, 1 }, /* 0xe3008000 */
-	{ TARGET_PCS10G_BR,           0x300c000, 1 }, /* 0xe300c000 */
-	{ TARGET_DEV2G5 +  1,         0x3010000, 1 }, /* 0xe3010000 */
-	{ TARGET_DEV2G5 +  2,         0x3014000, 1 }, /* 0xe3014000 */
-	{ TARGET_DEV2G5 +  3,         0x3018000, 1 }, /* 0xe3018000 */
-	{ TARGET_DEV2G5 +  4,         0x301c000, 1 }, /* 0xe301c000 */
-	{ TARGET_DEV10G +  1,         0x3020000, 1 }, /* 0xe3020000 */
-	{ TARGET_PCS10G_BR +  1,      0x3024000, 1 }, /* 0xe3024000 */
-	{ TARGET_DEV2G5 +  5,         0x3028000, 1 }, /* 0xe3028000 */
-	{ TARGET_DEV2G5 +  6,         0x302c000, 1 }, /* 0xe302c000 */
-	{ TARGET_DEV2G5 +  7,         0x3030000, 1 }, /* 0xe3030000 */
-	{ TARGET_DEV2G5 +  8,         0x3034000, 1 }, /* 0xe3034000 */
-	{ TARGET_DEV10G +  2,         0x3038000, 1 }, /* 0xe3038000 */
-	{ TARGET_PCS10G_BR +  2,      0x303c000, 1 }, /* 0xe303c000 */
-	{ TARGET_DEV2G5 +  9,         0x3040000, 1 }, /* 0xe3040000 */
-	{ TARGET_DEV5G,               0x3044000, 1 }, /* 0xe3044000 */
-	{ TARGET_PCS5G_BR,            0x3048000, 1 }, /* 0xe3048000 */
-	{ TARGET_DEV2G5 + 10,         0x304c000, 1 }, /* 0xe304c000 */
-	{ TARGET_DEV2G5 + 11,         0x3050000, 1 }, /* 0xe3050000 */
-	{ TARGET_DEV2G5 + 12,         0x3054000, 1 }, /* 0xe3054000 */
-	{ TARGET_DEV10G +  3,         0x3058000, 1 }, /* 0xe3058000 */
-	{ TARGET_PCS10G_BR +  3,      0x305c000, 1 }, /* 0xe305c000 */
-	{ TARGET_DEV2G5 + 13,         0x3060000, 1 }, /* 0xe3060000 */
-	{ TARGET_DEV5G +  1,          0x3064000, 1 }, /* 0xe3064000 */
-	{ TARGET_PCS5G_BR +  1,       0x3068000, 1 }, /* 0xe3068000 */
-	{ TARGET_DEV2G5 + 14,         0x306c000, 1 }, /* 0xe306c000 */
-	{ TARGET_DEV2G5 + 15,         0x3070000, 1 }, /* 0xe3070000 */
-	{ TARGET_DEV2G5 + 16,         0x3074000, 1 }, /* 0xe3074000 */
-	{ TARGET_DEV10G +  4,         0x3078000, 1 }, /* 0xe3078000 */
-	{ TARGET_PCS10G_BR +  4,      0x307c000, 1 }, /* 0xe307c000 */
-	{ TARGET_DEV2G5 + 17,         0x3080000, 1 }, /* 0xe3080000 */
-	{ TARGET_DEV5G +  2,          0x3084000, 1 }, /* 0xe3084000 */
-	{ TARGET_PCS5G_BR +  2,       0x3088000, 1 }, /* 0xe3088000 */
-	{ TARGET_DEV2G5 + 18,         0x308c000, 1 }, /* 0xe308c000 */
-	{ TARGET_DEV2G5 + 19,         0x3090000, 1 }, /* 0xe3090000 */
-	{ TARGET_DEV2G5 + 20,         0x3094000, 1 }, /* 0xe3094000 */
-	{ TARGET_DEV10G +  5,         0x3098000, 1 }, /* 0xe3098000 */
-	{ TARGET_PCS10G_BR +  5,      0x309c000, 1 }, /* 0xe309c000 */
-	{ TARGET_DEV2G5 + 21,         0x30a0000, 1 }, /* 0xe30a0000 */
-	{ TARGET_DEV5G +  3,          0x30a4000, 1 }, /* 0xe30a4000 */
-	{ TARGET_PCS5G_BR +  3,       0x30a8000, 1 }, /* 0xe30a8000 */
-	{ TARGET_DEV2G5 + 22,         0x30ac000, 1 }, /* 0xe30ac000 */
-	{ TARGET_DEV2G5 + 23,         0x30b0000, 1 }, /* 0xe30b0000 */
-	{ TARGET_DEV2G5 + 24,         0x30b4000, 1 }, /* 0xe30b4000 */
-	{ TARGET_DEV10G +  6,         0x30b8000, 1 }, /* 0xe30b8000 */
-	{ TARGET_PCS10G_BR +  6,      0x30bc000, 1 }, /* 0xe30bc000 */
-	{ TARGET_DEV2G5 + 25,         0x30c0000, 1 }, /* 0xe30c0000 */
-	{ TARGET_DEV10G +  7,         0x30c4000, 1 }, /* 0xe30c4000 */
-	{ TARGET_PCS10G_BR +  7,      0x30c8000, 1 }, /* 0xe30c8000 */
-	{ TARGET_DEV2G5 + 26,         0x30cc000, 1 }, /* 0xe30cc000 */
-	{ TARGET_DEV10G +  8,         0x30d0000, 1 }, /* 0xe30d0000 */
-	{ TARGET_PCS10G_BR +  8,      0x30d4000, 1 }, /* 0xe30d4000 */
-	{ TARGET_DEV2G5 + 27,         0x30d8000, 1 }, /* 0xe30d8000 */
-	{ TARGET_DEV10G +  9,         0x30dc000, 1 }, /* 0xe30dc000 */
-	{ TARGET_PCS10G_BR +  9,      0x30e0000, 1 }, /* 0xe30e0000 */
-	{ TARGET_DSM,                 0x30ec000, 1 }, /* 0xe30ec000 */
-	{ TARGET_PORT_CONF,           0x30f0000, 1 }, /* 0xe30f0000 */
-	{ TARGET_ASM,                 0x3200000, 1 }, /* 0xe3200000 */
-};
-
-static struct sparx5_sdlb_group lan969x_sdlb_groups[LAN969X_SDLB_GRP_CNT] = {
-	{ 1000000000,  8192 / 2, 64 }, /*    1 G */
-	{  500000000,  8192 / 2, 64 }, /*  500 M */
-	{  100000000,  8192 / 4, 64 }, /*  100 M */
-	{   50000000,  8192 / 4, 64 }, /*   50 M */
-	{    5000000,  8192 / 8, 64 }, /*   10 M */
-};
-
-static u32 lan969x_hsch_max_group_rate[LAN969X_HSCH_LEAK_GRP_CNT] = {
-	655355, 1048568, 6553550, 10485680
-};
-
-static struct sparx5_sdlb_group *lan969x_get_sdlb_group(int idx)
-{
-	return &lan969x_sdlb_groups[idx];
-}
-
-static u32 lan969x_get_hsch_max_group_rate(int grp)
-{
-	return lan969x_hsch_max_group_rate[grp];
-}
-
-static u32 lan969x_get_dev_mode_bit(struct sparx5 *sparx5, int port)
-{
-	if (lan969x_port_is_2g5(port) || lan969x_port_is_5g(port))
-		return port;
-
-	/* 10G */
-	switch (port) {
-	case 0:
-		return 12;
-	case 4:
-		return 13;
-	case 8:
-		return 14;
-	case 12:
-		return 0;
-	default:
-		return port;
-	}
-}
-
-static u32 lan969x_port_dev_mapping(struct sparx5 *sparx5, int port)
-{
-	if (lan969x_port_is_5g(port)) {
-		switch (port) {
-		case 9:
-			return 0;
-		case 13:
-			return 1;
-		case 17:
-			return 2;
-		case 21:
-			return 3;
-		}
-	}
-
-	if (lan969x_port_is_10g(port)) {
-		switch (port) {
-		case 0:
-			return 0;
-		case 4:
-			return 1;
-		case 8:
-			return 2;
-		case 12:
-			return 3;
-		case 16:
-			return 4;
-		case 20:
-			return 5;
-		case 24:
-			return 6;
-		case 25:
-			return 7;
-		case 26:
-			return 8;
-		case 27:
-			return 9;
-		}
-	}
-
-	/* 2g5 port */
-	return port;
-}
-
-static int lan969x_port_mux_set(struct sparx5 *sparx5, struct sparx5_port *port,
-				struct sparx5_port_config *conf)
-{
-	u32 portno = port->portno;
-	u32 inst;
-
-	if (port->conf.portmode == conf->portmode)
-		return 0; /* Nothing to do */
-
-	switch (conf->portmode) {
-	case PHY_INTERFACE_MODE_QSGMII: /* QSGMII: 4x2G5 devices. Mode Q'  */
-		inst = (portno - portno % 4) / 4;
-		spx5_rmw(BIT(inst), BIT(inst), sparx5, PORT_CONF_QSGMII_ENA);
-		break;
-	default:
-		break;
-	}
-	return 0;
-}
-
-static irqreturn_t lan969x_ptp_irq_handler(int irq, void *args)
-{
-	int budget = SPARX5_MAX_PTP_ID;
-	struct sparx5 *sparx5 = args;
-
-	while (budget--) {
-		struct sk_buff *skb, *skb_tmp, *skb_match = NULL;
-		struct skb_shared_hwtstamps shhwtstamps;
-		struct sparx5_port *port;
-		struct timespec64 ts;
-		unsigned long flags;
-		u32 val, id, txport;
-		u32 delay;
-
-		val = spx5_rd(sparx5, PTP_TWOSTEP_CTRL);
-
-		/* Check if a timestamp can be retrieved */
-		if (!(val & PTP_TWOSTEP_CTRL_PTP_VLD))
-			break;
-
-		WARN_ON(val & PTP_TWOSTEP_CTRL_PTP_OVFL);
-
-		if (!(val & PTP_TWOSTEP_CTRL_STAMP_TX))
-			continue;
-
-		/* Retrieve the ts Tx port */
-		txport = PTP_TWOSTEP_CTRL_STAMP_PORT_GET(val);
-
-		/* Retrieve its associated skb */
-		port = sparx5->ports[txport];
-
-		/* Retrieve the delay */
-		delay = spx5_rd(sparx5, PTP_TWOSTEP_STAMP_NSEC);
-		delay = PTP_TWOSTEP_STAMP_NSEC_NS_GET(delay);
-
-		/* Get next timestamp from fifo, which needs to be the
-		 * rx timestamp which represents the id of the frame
-		 */
-		spx5_rmw(PTP_TWOSTEP_CTRL_PTP_NXT_SET(1),
-			 PTP_TWOSTEP_CTRL_PTP_NXT,
-			 sparx5, PTP_TWOSTEP_CTRL);
-
-		val = spx5_rd(sparx5, PTP_TWOSTEP_CTRL);
-
-		/* Check if a timestamp can be retrieved */
-		if (!(val & PTP_TWOSTEP_CTRL_PTP_VLD))
-			break;
-
-		/* Read RX timestamping to get the ID */
-		id = spx5_rd(sparx5, PTP_TWOSTEP_STAMP_NSEC);
-		id <<= 8;
-		id |= spx5_rd(sparx5, PTP_TWOSTEP_STAMP_SUBNS);
-
-		spin_lock_irqsave(&port->tx_skbs.lock, flags);
-		skb_queue_walk_safe(&port->tx_skbs, skb, skb_tmp) {
-			if (SPARX5_SKB_CB(skb)->ts_id != id)
-				continue;
-
-			__skb_unlink(skb, &port->tx_skbs);
-			skb_match = skb;
-			break;
-		}
-		spin_unlock_irqrestore(&port->tx_skbs.lock, flags);
-
-		/* Next ts */
-		spx5_rmw(PTP_TWOSTEP_CTRL_PTP_NXT_SET(1),
-			 PTP_TWOSTEP_CTRL_PTP_NXT,
-			 sparx5, PTP_TWOSTEP_CTRL);
-
-		if (WARN_ON(!skb_match))
-			continue;
-
-		spin_lock(&sparx5->ptp_ts_id_lock);
-		sparx5->ptp_skbs--;
-		spin_unlock(&sparx5->ptp_ts_id_lock);
-
-		/* Get the h/w timestamp */
-		sparx5_get_hwtimestamp(sparx5, &ts, delay);
-
-		/* Set the timestamp in the skb */
-		shhwtstamps.hwtstamp = ktime_set(ts.tv_sec, ts.tv_nsec);
-		skb_tstamp_tx(skb_match, &shhwtstamps);
-
-		dev_kfree_skb_any(skb_match);
-	}
-
-	return IRQ_HANDLED;
-}
-
-static const struct sparx5_regs lan969x_regs = {
-	.tsize = lan969x_tsize,
-	.gaddr = lan969x_gaddr,
-	.gcnt  = lan969x_gcnt,
-	.gsize = lan969x_gsize,
-	.raddr = lan969x_raddr,
-	.rcnt  = lan969x_rcnt,
-	.fpos  = lan969x_fpos,
-	.fsize = lan969x_fsize,
-};
-
-static const struct sparx5_consts lan969x_consts = {
-	.n_ports             = 30,
-	.n_ports_all         = 35,
-	.n_hsch_l1_elems     = 32,
-	.n_hsch_queues       = 4,
-	.n_lb_groups         = 5,
-	.n_pgids             = 1054, /* (1024 + n_ports) */
-	.n_sio_clks          = 1,
-	.n_own_upsids        = 1,
-	.n_auto_cals         = 4,
-	.n_filters           = 256,
-	.n_gates             = 256,
-	.n_sdlbs             = 496,
-	.n_dsm_cal_taxis     = 5,
-	.buf_size            = 1572864,
-	.qres_max_prio_idx   = 315,
-	.qres_max_colour_idx = 323,
-	.tod_pin             = 4,
-	.vcaps               = lan969x_vcaps,
-	.vcap_stats          = &lan969x_vcap_stats,
-	.vcaps_cfg           = lan969x_vcap_inst_cfg,
-};
-
-static const struct sparx5_ops lan969x_ops = {
-	.is_port_2g5             = &lan969x_port_is_2g5,
-	.is_port_5g              = &lan969x_port_is_5g,
-	.is_port_10g             = &lan969x_port_is_10g,
-	.is_port_25g             = &lan969x_port_is_25g,
-	.get_port_dev_index      = &lan969x_port_dev_mapping,
-	.get_port_dev_bit        = &lan969x_get_dev_mode_bit,
-	.get_hsch_max_group_rate = &lan969x_get_hsch_max_group_rate,
-	.get_sdlb_group          = &lan969x_get_sdlb_group,
-	.set_port_mux            = &lan969x_port_mux_set,
-	.ptp_irq_handler         = &lan969x_ptp_irq_handler,
-	.dsm_calendar_calc       = &lan969x_dsm_calendar_calc,
-};
-
-const struct sparx5_match_data lan969x_desc = {
-	.iomap      = lan969x_main_iomap,
-	.iomap_size = ARRAY_SIZE(lan969x_main_iomap),
-	.ioranges   = 2,
-	.regs       = &lan969x_regs,
-	.consts     = &lan969x_consts,
-	.ops        = &lan969x_ops,
-};
-EXPORT_SYMBOL_GPL(lan969x_desc);
-
-MODULE_DESCRIPTION("Microchip lan969x switch driver");
-MODULE_AUTHOR("Daniel Machon <daniel.machon@microchip.com>");
-MODULE_LICENSE("Dual MIT/GPL");
--- /dev/null
+++ b/drivers/net/ethernet/microchip/sparx5/lan969x/lan969x.c
@@ -0,0 +1,348 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Microchip lan969x Switch driver
+ *
+ * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries.
+ */
+
+#include "lan969x.h"
+
+#define LAN969X_SDLB_GRP_CNT 5
+#define LAN969X_HSCH_LEAK_GRP_CNT 4
+
+static const struct sparx5_main_io_resource lan969x_main_iomap[] =  {
+	{ TARGET_CPU,                   0xc0000, 0 }, /* 0xe00c0000 */
+	{ TARGET_FDMA,                  0xc0400, 0 }, /* 0xe00c0400 */
+	{ TARGET_GCB,                 0x2010000, 1 }, /* 0xe2010000 */
+	{ TARGET_QS,                  0x2030000, 1 }, /* 0xe2030000 */
+	{ TARGET_PTP,                 0x2040000, 1 }, /* 0xe2040000 */
+	{ TARGET_ANA_ACL,             0x2050000, 1 }, /* 0xe2050000 */
+	{ TARGET_LRN,                 0x2060000, 1 }, /* 0xe2060000 */
+	{ TARGET_VCAP_SUPER,          0x2080000, 1 }, /* 0xe2080000 */
+	{ TARGET_QSYS,                0x20a0000, 1 }, /* 0xe20a0000 */
+	{ TARGET_QFWD,                0x20b0000, 1 }, /* 0xe20b0000 */
+	{ TARGET_XQS,                 0x20c0000, 1 }, /* 0xe20c0000 */
+	{ TARGET_VCAP_ES2,            0x20d0000, 1 }, /* 0xe20d0000 */
+	{ TARGET_VCAP_ES0,            0x20e0000, 1 }, /* 0xe20e0000 */
+	{ TARGET_ANA_AC_POL,          0x2200000, 1 }, /* 0xe2200000 */
+	{ TARGET_QRES,                0x2280000, 1 }, /* 0xe2280000 */
+	{ TARGET_EACL,                0x22c0000, 1 }, /* 0xe22c0000 */
+	{ TARGET_ANA_CL,              0x2400000, 1 }, /* 0xe2400000 */
+	{ TARGET_ANA_L3,              0x2480000, 1 }, /* 0xe2480000 */
+	{ TARGET_ANA_AC_SDLB,         0x2500000, 1 }, /* 0xe2500000 */
+	{ TARGET_HSCH,                0x2580000, 1 }, /* 0xe2580000 */
+	{ TARGET_REW,                 0x2600000, 1 }, /* 0xe2600000 */
+	{ TARGET_ANA_L2,              0x2800000, 1 }, /* 0xe2800000 */
+	{ TARGET_ANA_AC,              0x2900000, 1 }, /* 0xe2900000 */
+	{ TARGET_VOP,                 0x2a00000, 1 }, /* 0xe2a00000 */
+	{ TARGET_DEV2G5,              0x3004000, 1 }, /* 0xe3004000 */
+	{ TARGET_DEV10G,              0x3008000, 1 }, /* 0xe3008000 */
+	{ TARGET_PCS10G_BR,           0x300c000, 1 }, /* 0xe300c000 */
+	{ TARGET_DEV2G5 +  1,         0x3010000, 1 }, /* 0xe3010000 */
+	{ TARGET_DEV2G5 +  2,         0x3014000, 1 }, /* 0xe3014000 */
+	{ TARGET_DEV2G5 +  3,         0x3018000, 1 }, /* 0xe3018000 */
+	{ TARGET_DEV2G5 +  4,         0x301c000, 1 }, /* 0xe301c000 */
+	{ TARGET_DEV10G +  1,         0x3020000, 1 }, /* 0xe3020000 */
+	{ TARGET_PCS10G_BR +  1,      0x3024000, 1 }, /* 0xe3024000 */
+	{ TARGET_DEV2G5 +  5,         0x3028000, 1 }, /* 0xe3028000 */
+	{ TARGET_DEV2G5 +  6,         0x302c000, 1 }, /* 0xe302c000 */
+	{ TARGET_DEV2G5 +  7,         0x3030000, 1 }, /* 0xe3030000 */
+	{ TARGET_DEV2G5 +  8,         0x3034000, 1 }, /* 0xe3034000 */
+	{ TARGET_DEV10G +  2,         0x3038000, 1 }, /* 0xe3038000 */
+	{ TARGET_PCS10G_BR +  2,      0x303c000, 1 }, /* 0xe303c000 */
+	{ TARGET_DEV2G5 +  9,         0x3040000, 1 }, /* 0xe3040000 */
+	{ TARGET_DEV5G,               0x3044000, 1 }, /* 0xe3044000 */
+	{ TARGET_PCS5G_BR,            0x3048000, 1 }, /* 0xe3048000 */
+	{ TARGET_DEV2G5 + 10,         0x304c000, 1 }, /* 0xe304c000 */
+	{ TARGET_DEV2G5 + 11,         0x3050000, 1 }, /* 0xe3050000 */
+	{ TARGET_DEV2G5 + 12,         0x3054000, 1 }, /* 0xe3054000 */
+	{ TARGET_DEV10G +  3,         0x3058000, 1 }, /* 0xe3058000 */
+	{ TARGET_PCS10G_BR +  3,      0x305c000, 1 }, /* 0xe305c000 */
+	{ TARGET_DEV2G5 + 13,         0x3060000, 1 }, /* 0xe3060000 */
+	{ TARGET_DEV5G +  1,          0x3064000, 1 }, /* 0xe3064000 */
+	{ TARGET_PCS5G_BR +  1,       0x3068000, 1 }, /* 0xe3068000 */
+	{ TARGET_DEV2G5 + 14,         0x306c000, 1 }, /* 0xe306c000 */
+	{ TARGET_DEV2G5 + 15,         0x3070000, 1 }, /* 0xe3070000 */
+	{ TARGET_DEV2G5 + 16,         0x3074000, 1 }, /* 0xe3074000 */
+	{ TARGET_DEV10G +  4,         0x3078000, 1 }, /* 0xe3078000 */
+	{ TARGET_PCS10G_BR +  4,      0x307c000, 1 }, /* 0xe307c000 */
+	{ TARGET_DEV2G5 + 17,         0x3080000, 1 }, /* 0xe3080000 */
+	{ TARGET_DEV5G +  2,          0x3084000, 1 }, /* 0xe3084000 */
+	{ TARGET_PCS5G_BR +  2,       0x3088000, 1 }, /* 0xe3088000 */
+	{ TARGET_DEV2G5 + 18,         0x308c000, 1 }, /* 0xe308c000 */
+	{ TARGET_DEV2G5 + 19,         0x3090000, 1 }, /* 0xe3090000 */
+	{ TARGET_DEV2G5 + 20,         0x3094000, 1 }, /* 0xe3094000 */
+	{ TARGET_DEV10G +  5,         0x3098000, 1 }, /* 0xe3098000 */
+	{ TARGET_PCS10G_BR +  5,      0x309c000, 1 }, /* 0xe309c000 */
+	{ TARGET_DEV2G5 + 21,         0x30a0000, 1 }, /* 0xe30a0000 */
+	{ TARGET_DEV5G +  3,          0x30a4000, 1 }, /* 0xe30a4000 */
+	{ TARGET_PCS5G_BR +  3,       0x30a8000, 1 }, /* 0xe30a8000 */
+	{ TARGET_DEV2G5 + 22,         0x30ac000, 1 }, /* 0xe30ac000 */
+	{ TARGET_DEV2G5 + 23,         0x30b0000, 1 }, /* 0xe30b0000 */
+	{ TARGET_DEV2G5 + 24,         0x30b4000, 1 }, /* 0xe30b4000 */
+	{ TARGET_DEV10G +  6,         0x30b8000, 1 }, /* 0xe30b8000 */
+	{ TARGET_PCS10G_BR +  6,      0x30bc000, 1 }, /* 0xe30bc000 */
+	{ TARGET_DEV2G5 + 25,         0x30c0000, 1 }, /* 0xe30c0000 */
+	{ TARGET_DEV10G +  7,         0x30c4000, 1 }, /* 0xe30c4000 */
+	{ TARGET_PCS10G_BR +  7,      0x30c8000, 1 }, /* 0xe30c8000 */
+	{ TARGET_DEV2G5 + 26,         0x30cc000, 1 }, /* 0xe30cc000 */
+	{ TARGET_DEV10G +  8,         0x30d0000, 1 }, /* 0xe30d0000 */
+	{ TARGET_PCS10G_BR +  8,      0x30d4000, 1 }, /* 0xe30d4000 */
+	{ TARGET_DEV2G5 + 27,         0x30d8000, 1 }, /* 0xe30d8000 */
+	{ TARGET_DEV10G +  9,         0x30dc000, 1 }, /* 0xe30dc000 */
+	{ TARGET_PCS10G_BR +  9,      0x30e0000, 1 }, /* 0xe30e0000 */
+	{ TARGET_DSM,                 0x30ec000, 1 }, /* 0xe30ec000 */
+	{ TARGET_PORT_CONF,           0x30f0000, 1 }, /* 0xe30f0000 */
+	{ TARGET_ASM,                 0x3200000, 1 }, /* 0xe3200000 */
+};
+
+static struct sparx5_sdlb_group lan969x_sdlb_groups[LAN969X_SDLB_GRP_CNT] = {
+	{ 1000000000,  8192 / 2, 64 }, /*    1 G */
+	{  500000000,  8192 / 2, 64 }, /*  500 M */
+	{  100000000,  8192 / 4, 64 }, /*  100 M */
+	{   50000000,  8192 / 4, 64 }, /*   50 M */
+	{    5000000,  8192 / 8, 64 }, /*   10 M */
+};
+
+static u32 lan969x_hsch_max_group_rate[LAN969X_HSCH_LEAK_GRP_CNT] = {
+	655355, 1048568, 6553550, 10485680
+};
+
+static struct sparx5_sdlb_group *lan969x_get_sdlb_group(int idx)
+{
+	return &lan969x_sdlb_groups[idx];
+}
+
+static u32 lan969x_get_hsch_max_group_rate(int grp)
+{
+	return lan969x_hsch_max_group_rate[grp];
+}
+
+static u32 lan969x_get_dev_mode_bit(struct sparx5 *sparx5, int port)
+{
+	if (lan969x_port_is_2g5(port) || lan969x_port_is_5g(port))
+		return port;
+
+	/* 10G */
+	switch (port) {
+	case 0:
+		return 12;
+	case 4:
+		return 13;
+	case 8:
+		return 14;
+	case 12:
+		return 0;
+	default:
+		return port;
+	}
+}
+
+static u32 lan969x_port_dev_mapping(struct sparx5 *sparx5, int port)
+{
+	if (lan969x_port_is_5g(port)) {
+		switch (port) {
+		case 9:
+			return 0;
+		case 13:
+			return 1;
+		case 17:
+			return 2;
+		case 21:
+			return 3;
+		}
+	}
+
+	if (lan969x_port_is_10g(port)) {
+		switch (port) {
+		case 0:
+			return 0;
+		case 4:
+			return 1;
+		case 8:
+			return 2;
+		case 12:
+			return 3;
+		case 16:
+			return 4;
+		case 20:
+			return 5;
+		case 24:
+			return 6;
+		case 25:
+			return 7;
+		case 26:
+			return 8;
+		case 27:
+			return 9;
+		}
+	}
+
+	/* 2g5 port */
+	return port;
+}
+
+static int lan969x_port_mux_set(struct sparx5 *sparx5, struct sparx5_port *port,
+				struct sparx5_port_config *conf)
+{
+	u32 portno = port->portno;
+	u32 inst;
+
+	if (port->conf.portmode == conf->portmode)
+		return 0; /* Nothing to do */
+
+	switch (conf->portmode) {
+	case PHY_INTERFACE_MODE_QSGMII: /* QSGMII: 4x2G5 devices. Mode Q'  */
+		inst = (portno - portno % 4) / 4;
+		spx5_rmw(BIT(inst), BIT(inst), sparx5, PORT_CONF_QSGMII_ENA);
+		break;
+	default:
+		break;
+	}
+	return 0;
+}
+
+static irqreturn_t lan969x_ptp_irq_handler(int irq, void *args)
+{
+	int budget = SPARX5_MAX_PTP_ID;
+	struct sparx5 *sparx5 = args;
+
+	while (budget--) {
+		struct sk_buff *skb, *skb_tmp, *skb_match = NULL;
+		struct skb_shared_hwtstamps shhwtstamps;
+		struct sparx5_port *port;
+		struct timespec64 ts;
+		unsigned long flags;
+		u32 val, id, txport;
+		u32 delay;
+
+		val = spx5_rd(sparx5, PTP_TWOSTEP_CTRL);
+
+		/* Check if a timestamp can be retrieved */
+		if (!(val & PTP_TWOSTEP_CTRL_PTP_VLD))
+			break;
+
+		WARN_ON(val & PTP_TWOSTEP_CTRL_PTP_OVFL);
+
+		if (!(val & PTP_TWOSTEP_CTRL_STAMP_TX))
+			continue;
+
+		/* Retrieve the ts Tx port */
+		txport = PTP_TWOSTEP_CTRL_STAMP_PORT_GET(val);
+
+		/* Retrieve its associated skb */
+		port = sparx5->ports[txport];
+
+		/* Retrieve the delay */
+		delay = spx5_rd(sparx5, PTP_TWOSTEP_STAMP_NSEC);
+		delay = PTP_TWOSTEP_STAMP_NSEC_NS_GET(delay);
+
+		/* Get next timestamp from fifo, which needs to be the
+		 * rx timestamp which represents the id of the frame
+		 */
+		spx5_rmw(PTP_TWOSTEP_CTRL_PTP_NXT_SET(1),
+			 PTP_TWOSTEP_CTRL_PTP_NXT,
+			 sparx5, PTP_TWOSTEP_CTRL);
+
+		val = spx5_rd(sparx5, PTP_TWOSTEP_CTRL);
+
+		/* Check if a timestamp can be retrieved */
+		if (!(val & PTP_TWOSTEP_CTRL_PTP_VLD))
+			break;
+
+		/* Read RX timestamping to get the ID */
+		id = spx5_rd(sparx5, PTP_TWOSTEP_STAMP_NSEC);
+		id <<= 8;
+		id |= spx5_rd(sparx5, PTP_TWOSTEP_STAMP_SUBNS);
+
+		spin_lock_irqsave(&port->tx_skbs.lock, flags);
+		skb_queue_walk_safe(&port->tx_skbs, skb, skb_tmp) {
+			if (SPARX5_SKB_CB(skb)->ts_id != id)
+				continue;
+
+			__skb_unlink(skb, &port->tx_skbs);
+			skb_match = skb;
+			break;
+		}
+		spin_unlock_irqrestore(&port->tx_skbs.lock, flags);
+
+		/* Next ts */
+		spx5_rmw(PTP_TWOSTEP_CTRL_PTP_NXT_SET(1),
+			 PTP_TWOSTEP_CTRL_PTP_NXT,
+			 sparx5, PTP_TWOSTEP_CTRL);
+
+		if (WARN_ON(!skb_match))
+			continue;
+
+		spin_lock(&sparx5->ptp_ts_id_lock);
+		sparx5->ptp_skbs--;
+		spin_unlock(&sparx5->ptp_ts_id_lock);
+
+		/* Get the h/w timestamp */
+		sparx5_get_hwtimestamp(sparx5, &ts, delay);
+
+		/* Set the timestamp in the skb */
+		shhwtstamps.hwtstamp = ktime_set(ts.tv_sec, ts.tv_nsec);
+		skb_tstamp_tx(skb_match, &shhwtstamps);
+
+		dev_kfree_skb_any(skb_match);
+	}
+
+	return IRQ_HANDLED;
+}
+
+static const struct sparx5_regs lan969x_regs = {
+	.tsize = lan969x_tsize,
+	.gaddr = lan969x_gaddr,
+	.gcnt  = lan969x_gcnt,
+	.gsize = lan969x_gsize,
+	.raddr = lan969x_raddr,
+	.rcnt  = lan969x_rcnt,
+	.fpos  = lan969x_fpos,
+	.fsize = lan969x_fsize,
+};
+
+static const struct sparx5_consts lan969x_consts = {
+	.n_ports             = 30,
+	.n_ports_all         = 35,
+	.n_hsch_l1_elems     = 32,
+	.n_hsch_queues       = 4,
+	.n_lb_groups         = 5,
+	.n_pgids             = 1054, /* (1024 + n_ports) */
+	.n_sio_clks          = 1,
+	.n_own_upsids        = 1,
+	.n_auto_cals         = 4,
+	.n_filters           = 256,
+	.n_gates             = 256,
+	.n_sdlbs             = 496,
+	.n_dsm_cal_taxis     = 5,
+	.buf_size            = 1572864,
+	.qres_max_prio_idx   = 315,
+	.qres_max_colour_idx = 323,
+	.tod_pin             = 4,
+	.vcaps               = lan969x_vcaps,
+	.vcap_stats          = &lan969x_vcap_stats,
+	.vcaps_cfg           = lan969x_vcap_inst_cfg,
+};
+
+static const struct sparx5_ops lan969x_ops = {
+	.is_port_2g5             = &lan969x_port_is_2g5,
+	.is_port_5g              = &lan969x_port_is_5g,
+	.is_port_10g             = &lan969x_port_is_10g,
+	.is_port_25g             = &lan969x_port_is_25g,
+	.get_port_dev_index      = &lan969x_port_dev_mapping,
+	.get_port_dev_bit        = &lan969x_get_dev_mode_bit,
+	.get_hsch_max_group_rate = &lan969x_get_hsch_max_group_rate,
+	.get_sdlb_group          = &lan969x_get_sdlb_group,
+	.set_port_mux            = &lan969x_port_mux_set,
+	.ptp_irq_handler         = &lan969x_ptp_irq_handler,
+	.dsm_calendar_calc       = &lan969x_dsm_calendar_calc,
+};
+
+const struct sparx5_match_data lan969x_desc = {
+	.iomap      = lan969x_main_iomap,
+	.iomap_size = ARRAY_SIZE(lan969x_main_iomap),
+	.ioranges   = 2,
+	.regs       = &lan969x_regs,
+	.consts     = &lan969x_consts,
+	.ops        = &lan969x_ops,
+};
--- a/drivers/net/ethernet/microchip/sparx5/sparx5_calendar.c
+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_calendar.c
@@ -98,7 +98,6 @@ u32 sparx5_cal_speed_to_value(enum sparx
 	default: return 0;
 	}
 }
-EXPORT_SYMBOL_GPL(sparx5_cal_speed_to_value);
 
 static u32 sparx5_bandwidth_to_calendar(u32 bw)
 {
@@ -150,7 +149,6 @@ enum sparx5_cal_bw sparx5_get_port_cal_s
 		return SPX5_CAL_SPEED_NONE;
 	return sparx5_bandwidth_to_calendar(port->conf.bandwidth);
 }
-EXPORT_SYMBOL_GPL(sparx5_get_port_cal_speed);
 
 /* Auto configure the QSYS calendar based on port configuration */
 int sparx5_config_auto_calendar(struct sparx5 *sparx5)
--- a/drivers/net/ethernet/microchip/sparx5/sparx5_main.c
+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_main.c
@@ -24,7 +24,7 @@
 #include <linux/types.h>
 #include <linux/reset.h>
 
-#include "../lan969x/lan969x.h" /* for lan969x match data */
+#include "lan969x/lan969x.h" /* for lan969x match data */
 
 #include "sparx5_main_regs.h"
 #include "sparx5_main.h"
@@ -1092,7 +1092,7 @@ static const struct sparx5_match_data sp
 
 static const struct of_device_id mchp_sparx5_match[] = {
 	{ .compatible = "microchip,sparx5-switch", .data = &sparx5_desc },
-#if IS_ENABLED(CONFIG_LAN969X_SWITCH)
+#ifdef CONFIG_LAN969X_SWITCH
 	{ .compatible = "microchip,lan9691-switch", .data = &lan969x_desc },
 #endif
 	{ }
--- a/drivers/net/ethernet/microchip/sparx5/sparx5_ptp.c
+++ b/drivers/net/ethernet/microchip/sparx5/sparx5_ptp.c
@@ -303,7 +303,6 @@ void sparx5_get_hwtimestamp(struct sparx
 
 	spin_unlock_irqrestore(&sparx5->ptp_clock_lock, flags);
 }
-EXPORT_SYMBOL_GPL(sparx5_get_hwtimestamp);
 
 irqreturn_t sparx5_ptp_irq_handler(int irq, void *args)
 {
--- a/drivers/net/ethernet/microchip/lan969x/lan969x.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
-/* Microchip lan969x Switch driver
- *
- * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries.
- */
-
-#ifndef __LAN969X_H__
-#define __LAN969X_H__
-
-#include "../sparx5/sparx5_main.h"
-#include "../sparx5/sparx5_regs.h"
-#include "../sparx5/sparx5_vcap_impl.h"
-
-/* lan969x.c */
-extern const struct sparx5_match_data lan969x_desc;
-
-/* lan969x_vcap_ag_api.c */
-extern const struct vcap_statistics lan969x_vcap_stats;
-extern const struct vcap_info lan969x_vcaps[];
-
-/* lan969x_vcap_impl.c */
-extern const struct sparx5_vcap_inst lan969x_vcap_inst_cfg[];
-
-/* lan969x_regs.c */
-extern const unsigned int lan969x_tsize[TSIZE_LAST];
-extern const unsigned int lan969x_raddr[RADDR_LAST];
-extern const unsigned int lan969x_rcnt[RCNT_LAST];
-extern const unsigned int lan969x_gaddr[GADDR_LAST];
-extern const unsigned int lan969x_gcnt[GCNT_LAST];
-extern const unsigned int lan969x_gsize[GSIZE_LAST];
-extern const unsigned int lan969x_fpos[FPOS_LAST];
-extern const unsigned int lan969x_fsize[FSIZE_LAST];
-
-static inline bool lan969x_port_is_2g5(int portno)
-{
-	return portno == 1  || portno == 2  || portno == 3  ||
-	       portno == 5  || portno == 6  || portno == 7  ||
-	       portno == 10 || portno == 11 || portno == 14 ||
-	       portno == 15 || portno == 18 || portno == 19 ||
-	       portno == 22 || portno == 23;
-}
-
-static inline bool lan969x_port_is_5g(int portno)
-{
-	return portno == 9 || portno == 13 || portno == 17 ||
-	       portno == 21;
-}
-
-static inline bool lan969x_port_is_10g(int portno)
-{
-	return portno == 0  || portno == 4  || portno == 8  ||
-	       portno == 12 || portno == 16 || portno == 20 ||
-	       portno == 24 || portno == 25 || portno == 26 ||
-	       portno == 27;
-}
-
-static inline bool lan969x_port_is_25g(int portno)
-{
-	return false;
-}
-
-/* lan969x_calendar.c */
-int lan969x_dsm_calendar_calc(struct sparx5 *sparx5, u32 taxi,
-			      struct sparx5_calendar_data *data);
-#endif
--- a/drivers/net/ethernet/microchip/lan969x/lan969x_calendar.c
+++ /dev/null
@@ -1,191 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/* Microchip lan969x Switch driver
- *
- * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries.
- */
-
-#include "lan969x.h"
-
-#define LAN969X_DSM_CAL_DEVS_PER_TAXI 10
-#define LAN969X_DSM_CAL_TAXIS 5
-
-enum lan969x_dsm_cal_dev {
-	DSM_CAL_DEV_2G5,
-	DSM_CAL_DEV_5G,
-	DSM_CAL_DEV_10G,
-	DSM_CAL_DEV_OTHER, /* 1G or less */
-	DSM_CAL_DEV_MAX
-};
-
-/* Each entry in the following struct defines properties for a given speed
- * (10G, 5G, 2.5G, or 1G or less).
- */
-struct lan969x_dsm_cal_dev_speed {
-	/* Number of devices that requires this speed. */
-	u32 n_devs;
-
-	/* Array of devices that requires this speed. */
-	u32 devs[LAN969X_DSM_CAL_DEVS_PER_TAXI];
-
-	/* Number of slots required for one device running this speed. */
-	u32 n_slots;
-
-	/* Gap between two slots for one device running this speed. */
-	u32 gap;
-};
-
-static u32
-lan969x_taxi_ports[LAN969X_DSM_CAL_TAXIS][LAN969X_DSM_CAL_DEVS_PER_TAXI] = {
-	{  0,  4,  1,  2,  3,  5,  6,  7, 28, 29 },
-	{  8, 12,  9, 13, 10, 11, 14, 15, 99, 99 },
-	{ 16, 20, 17, 21, 18, 19, 22, 23, 99, 99 },
-	{ 24, 25, 99, 99, 99, 99, 99, 99, 99, 99 },
-	{ 26, 27, 99, 99, 99, 99, 99, 99, 99, 99 }
-};
-
-static int lan969x_dsm_cal_idx_get(u32 *calendar, u32 cal_len, u32 *cal_idx)
-{
-	if (*cal_idx >= cal_len)
-		return -EINVAL;
-
-	do {
-		if (calendar[*cal_idx] == SPX5_DSM_CAL_EMPTY)
-			return 0;
-
-		(*cal_idx)++;
-	} while (*cal_idx < cal_len);
-
-	return -ENOENT;
-}
-
-static enum lan969x_dsm_cal_dev lan969x_dsm_cal_get_dev(int speed)
-{
-	return (speed == 10000 ? DSM_CAL_DEV_10G :
-		speed == 5000  ? DSM_CAL_DEV_5G :
-		speed == 2500  ? DSM_CAL_DEV_2G5 :
-				 DSM_CAL_DEV_OTHER);
-}
-
-static int lan969x_dsm_cal_get_speed(enum lan969x_dsm_cal_dev dev)
-{
-	return (dev == DSM_CAL_DEV_10G ? 10000 :
-		dev == DSM_CAL_DEV_5G  ? 5000 :
-		dev == DSM_CAL_DEV_2G5 ? 2500 :
-					 1000);
-}
-
-int lan969x_dsm_calendar_calc(struct sparx5 *sparx5, u32 taxi,
-			      struct sparx5_calendar_data *data)
-{
-	struct lan969x_dsm_cal_dev_speed dev_speeds[DSM_CAL_DEV_MAX] = {};
-	u32 cal_len, n_slots, taxi_bw, n_devs = 0, required_bw  = 0;
-	struct lan969x_dsm_cal_dev_speed *speed;
-	int err;
-
-	/* Maximum bandwidth for this taxi */
-	taxi_bw = (128 * 1000000) / sparx5_clk_period(sparx5->coreclock);
-
-	memcpy(data->taxi_ports, &lan969x_taxi_ports[taxi],
-	       LAN969X_DSM_CAL_DEVS_PER_TAXI * sizeof(u32));
-
-	for (int i = 0; i < LAN969X_DSM_CAL_DEVS_PER_TAXI; i++) {
-		u32 portno = data->taxi_ports[i];
-		enum sparx5_cal_bw bw;
-
-		bw = sparx5_get_port_cal_speed(sparx5, portno);
-
-		if (portno < sparx5->data->consts->n_ports_all)
-			data->taxi_speeds[i] = sparx5_cal_speed_to_value(bw);
-		else
-			data->taxi_speeds[i] = 0;
-	}
-
-	/* Determine the different port types (10G, 5G, 2.5G, <= 1G) in the
-	 * this taxi map.
-	 */
-	for (int i = 0; i < LAN969X_DSM_CAL_DEVS_PER_TAXI; i++) {
-		u32 taxi_speed = data->taxi_speeds[i];
-		enum lan969x_dsm_cal_dev dev;
-
-		if (taxi_speed == 0)
-			continue;
-
-		required_bw += taxi_speed;
-
-		dev = lan969x_dsm_cal_get_dev(taxi_speed);
-		speed = &dev_speeds[dev];
-		speed->devs[speed->n_devs++] = i;
-		n_devs++;
-	}
-
-	if (required_bw > taxi_bw) {
-		pr_err("Required bandwidth: %u is higher than total taxi bandwidth: %u",
-		       required_bw, taxi_bw);
-		return -EINVAL;
-	}
-
-	if (n_devs == 0) {
-		data->schedule[0] = SPX5_DSM_CAL_EMPTY;
-		return 0;
-	}
-
-	cal_len = n_devs;
-
-	/* Search for a calendar length that fits all active devices. */
-	while (cal_len < SPX5_DSM_CAL_LEN) {
-		u32 bw_per_slot = taxi_bw / cal_len;
-
-		n_slots = 0;
-
-		for (int i = 0; i < DSM_CAL_DEV_MAX; i++) {
-			speed = &dev_speeds[i];
-
-			if (speed->n_devs == 0)
-				continue;
-
-			required_bw = lan969x_dsm_cal_get_speed(i);
-			speed->n_slots = DIV_ROUND_UP(required_bw, bw_per_slot);
-
-			if (speed->n_slots)
-				speed->gap = DIV_ROUND_UP(cal_len,
-							  speed->n_slots);
-			else
-				speed->gap = 0;
-
-			n_slots += speed->n_slots * speed->n_devs;
-		}
-
-		if (n_slots <= cal_len)
-			break; /* Found a suitable calendar length. */
-
-		/* Not good enough yet. */
-		cal_len = n_slots;
-	}
-
-	if (cal_len > SPX5_DSM_CAL_LEN) {
-		pr_err("Invalid length: %u for taxi: %u", cal_len, taxi);
-		return -EINVAL;
-	}
-
-	for (u32 i = 0; i < SPX5_DSM_CAL_LEN; i++)
-		data->schedule[i] = SPX5_DSM_CAL_EMPTY;
-
-	/* Place the remaining devices */
-	for (u32 i = 0; i < DSM_CAL_DEV_MAX; i++) {
-		speed = &dev_speeds[i];
-		for (u32 dev = 0; dev < speed->n_devs; dev++) {
-			u32 idx = 0;
-
-			for (n_slots = 0; n_slots < speed->n_slots; n_slots++) {
-				err = lan969x_dsm_cal_idx_get(data->schedule,
-							      cal_len, &idx);
-				if (err)
-					return err;
-				data->schedule[idx] = speed->devs[dev];
-				idx += speed->gap;
-			}
-		}
-	}
-
-	return 0;
-}
--- a/drivers/net/ethernet/microchip/lan969x/lan969x_regs.c
+++ /dev/null
@@ -1,222 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/* Microchip lan969x Switch driver
- *
- * Copyright (c) 2024 Microchip Technology Inc.
- */
-
-/* This file is autogenerated by cml-utils 2024-09-30 11:48:29 +0200.
- * Commit ID: 9d07b8d19363f3cd3590ddb3f7a2e2768e16524b
- */
-
-#include "lan969x.h"
-
-const unsigned int lan969x_tsize[TSIZE_LAST] = {
-	[TC_DEV10G] = 10,
-	[TC_DEV2G5] = 28,
-	[TC_DEV5G] = 4,
-	[TC_PCS10G_BR] = 10,
-	[TC_PCS5G_BR] = 4,
-};
-
-const unsigned int lan969x_raddr[RADDR_LAST] = {
-	[RA_CPU_PROC_CTRL] = 160,
-	[RA_GCB_SOFT_RST] = 12,
-	[RA_GCB_HW_SGPIO_TO_SD_MAP_CFG] = 20,
-};
-
-const unsigned int lan969x_rcnt[RCNT_LAST] = {
-	[RC_ANA_AC_OWN_UPSID] = 1,
-	[RC_ANA_ACL_VCAP_S2_CFG] = 35,
-	[RC_ANA_ACL_OWN_UPSID] = 1,
-	[RC_ANA_CL_OWN_UPSID] = 1,
-	[RC_ANA_L2_OWN_UPSID] = 1,
-	[RC_ASM_PORT_CFG] = 32,
-	[RC_DSM_BUF_CFG] = 32,
-	[RC_DSM_DEV_TX_STOP_WM_CFG] = 32,
-	[RC_DSM_RX_PAUSE_CFG] = 32,
-	[RC_DSM_MAC_CFG] = 32,
-	[RC_DSM_MAC_ADDR_BASE_HIGH_CFG] = 30,
-	[RC_DSM_MAC_ADDR_BASE_LOW_CFG] = 30,
-	[RC_DSM_TAXI_CAL_CFG] = 6,
-	[RC_GCB_HW_SGPIO_TO_SD_MAP_CFG] = 30,
-	[RC_HSCH_PORT_MODE] = 35,
-	[RC_QFWD_SWITCH_PORT_MODE] = 35,
-	[RC_QSYS_PAUSE_CFG] = 35,
-	[RC_QSYS_ATOP] = 35,
-	[RC_QSYS_FWD_PRESSURE] = 35,
-	[RC_QSYS_CAL_AUTO] = 4,
-	[RC_REW_OWN_UPSID] = 1,
-	[RC_REW_RTAG_ETAG_CTRL] = 35,
-};
-
-const unsigned int lan969x_gaddr[GADDR_LAST] = {
-	[GA_ANA_AC_RAM_CTRL] = 202000,
-	[GA_ANA_AC_PS_COMMON] = 202880,
-	[GA_ANA_AC_MIRROR_PROBE] = 203232,
-	[GA_ANA_AC_SRC] = 201728,
-	[GA_ANA_AC_PGID] = 131072,
-	[GA_ANA_AC_TSN_SF] = 202028,
-	[GA_ANA_AC_TSN_SF_CFG] = 148480,
-	[GA_ANA_AC_TSN_SF_STATUS] = 147936,
-	[GA_ANA_AC_SG_ACCESS] = 202032,
-	[GA_ANA_AC_SG_CONFIG] = 202752,
-	[GA_ANA_AC_SG_STATUS] = 147952,
-	[GA_ANA_AC_SG_STATUS_STICKY] = 202044,
-	[GA_ANA_AC_STAT_GLOBAL_CFG_PORT] = 202048,
-	[GA_ANA_AC_STAT_CNT_CFG_PORT] = 204800,
-	[GA_ANA_AC_STAT_GLOBAL_CFG_ACL] = 202068,
-	[GA_ANA_ACL_COMMON] = 8192,
-	[GA_ANA_ACL_KEY_SEL] = 9204,
-	[GA_ANA_ACL_CNT_B] = 4096,
-	[GA_ANA_ACL_STICKY] = 10852,
-	[GA_ANA_AC_POL_POL_ALL_CFG] = 17504,
-	[GA_ANA_AC_POL_COMMON_BDLB] = 19464,
-	[GA_ANA_AC_POL_COMMON_BUM_SLB] = 19472,
-	[GA_ANA_AC_SDLB_LBGRP_TBL] = 31788,
-	[GA_ANA_CL_PORT] = 65536,
-	[GA_ANA_CL_COMMON] = 87040,
-	[GA_ANA_L2_COMMON] = 561928,
-	[GA_ANA_L3_COMMON] = 370752,
-	[GA_ANA_L3_VLAN_ARP_L3MC_STICKY] = 368580,
-	[GA_ASM_CFG] = 18304,
-	[GA_ASM_PFC_TIMER_CFG] = 15568,
-	[GA_ASM_LBK_WM_CFG] = 15596,
-	[GA_ASM_LBK_MISC_CFG] = 15608,
-	[GA_ASM_RAM_CTRL] = 15684,
-	[GA_EACL_ES2_KEY_SELECT_PROFILE] = 36864,
-	[GA_EACL_CNT_TBL] = 30720,
-	[GA_EACL_POL_CFG] = 38400,
-	[GA_EACL_ES2_STICKY] = 29072,
-	[GA_EACL_RAM_CTRL] = 29112,
-	[GA_GCB_SIO_CTRL] = 560,
-	[GA_HSCH_HSCH_DWRR] = 36480,
-	[GA_HSCH_HSCH_MISC] = 36608,
-	[GA_HSCH_HSCH_LEAK_LISTS] = 37256,
-	[GA_HSCH_SYSTEM] = 37384,
-	[GA_HSCH_MMGT] = 36260,
-	[GA_HSCH_TAS_CONFIG] = 37696,
-	[GA_PTP_PTP_CFG] = 512,
-	[GA_PTP_PTP_TOD_DOMAINS] = 528,
-	[GA_PTP_PHASE_DETECTOR_CTRL] = 628,
-	[GA_QSYS_CALCFG] = 2164,
-	[GA_QSYS_RAM_CTRL] = 2204,
-	[GA_REW_COMMON] = 98304,
-	[GA_REW_PORT] = 49152,
-	[GA_REW_VOE_PORT_LM_CNT] = 90112,
-	[GA_REW_RAM_CTRL] = 93992,
-	[GA_VOP_RAM_CTRL] = 16368,
-	[GA_XQS_SYSTEM] = 5744,
-	[GA_XQS_QLIMIT_SHR] = 6912,
-};
-
-const unsigned int lan969x_gcnt[GCNT_LAST] = {
-	[GC_ANA_AC_SRC] = 67,
-	[GC_ANA_AC_PGID] = 1054,
-	[GC_ANA_AC_TSN_SF_CFG] = 256,
-	[GC_ANA_AC_STAT_CNT_CFG_PORT] = 35,
-	[GC_ANA_ACL_KEY_SEL] = 99,
-	[GC_ANA_ACL_CNT_A] = 1024,
-	[GC_ANA_ACL_CNT_B] = 1024,
-	[GC_ANA_AC_SDLB_LBGRP_TBL] = 5,
-	[GC_ANA_AC_SDLB_LBSET_TBL] = 496,
-	[GC_ANA_CL_PORT] = 35,
-	[GC_ANA_L2_ISDX_LIMIT] = 256,
-	[GC_ANA_L2_ISDX] = 1024,
-	[GC_ANA_L3_VLAN] = 4608,
-	[GC_ASM_DEV_STATISTICS] = 30,
-	[GC_EACL_ES2_KEY_SELECT_PROFILE] = 68,
-	[GC_EACL_CNT_TBL] = 512,
-	[GC_GCB_SIO_CTRL] = 1,
-	[GC_HSCH_HSCH_CFG] = 1120,
-	[GC_HSCH_HSCH_DWRR] = 32,
-	[GC_PTP_PTP_PINS] = 8,
-	[GC_PTP_PHASE_DETECTOR_CTRL] = 8,
-	[GC_REW_PORT] = 35,
-	[GC_REW_VOE_PORT_LM_CNT] = 240,
-};
-
-const unsigned int lan969x_gsize[GSIZE_LAST] = {
-	[GW_ANA_AC_SRC] = 4,
-	[GW_ANA_L2_COMMON] = 712,
-	[GW_ASM_CFG] = 1092,
-	[GW_CPU_CPU_REGS] = 180,
-	[GW_DEV2G5_PHASE_DETECTOR_CTRL] = 12,
-	[GW_FDMA_FDMA] = 448,
-	[GW_GCB_CHIP_REGS] = 180,
-	[GW_HSCH_TAS_CONFIG] = 16,
-	[GW_PTP_PHASE_DETECTOR_CTRL] = 12,
-	[GW_QSYS_PAUSE_CFG] = 988,
-};
-
-const unsigned int lan969x_fpos[FPOS_LAST] = {
-	[FP_CPU_PROC_CTRL_AARCH64_MODE_ENA] = 7,
-	[FP_CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS] = 6,
-	[FP_CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS] = 5,
-	[FP_CPU_PROC_CTRL_BE_EXCEP_MODE] = 4,
-	[FP_CPU_PROC_CTRL_VINITHI] = 3,
-	[FP_CPU_PROC_CTRL_CFGTE] = 2,
-	[FP_CPU_PROC_CTRL_CP15S_DISABLE] = 1,
-	[FP_CPU_PROC_CTRL_PROC_CRYPTO_DISABLE] = 0,
-	[FP_CPU_PROC_CTRL_L2_FLUSH_REQ] = 8,
-	[FP_DEV2G5_PHAD_CTRL_PHAD_ENA] = 5,
-	[FP_DEV2G5_PHAD_CTRL_PHAD_FAILED] = 3,
-	[FP_FDMA_CH_CFG_CH_XTR_STATUS_MODE] = 5,
-	[FP_FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY] = 4,
-	[FP_FDMA_CH_CFG_CH_INJ_PORT] = 3,
-	[FP_PTP_PTP_PIN_CFG_PTP_PIN_ACTION] = 27,
-	[FP_PTP_PTP_PIN_CFG_PTP_PIN_SYNC] = 25,
-	[FP_PTP_PTP_PIN_CFG_PTP_PIN_INV_POL] = 24,
-	[FP_PTP_PHAD_CTRL_PHAD_ENA] = 5,
-	[FP_PTP_PHAD_CTRL_PHAD_FAILED] = 3,
-};
-
-const unsigned int lan969x_fsize[FSIZE_LAST] = {
-	[FW_ANA_AC_PROBE_PORT_CFG_PROBE_PORT_MASK] = 30,
-	[FW_ANA_AC_SRC_CFG_PORT_MASK] = 30,
-	[FW_ANA_AC_PGID_CFG_PORT_MASK] = 30,
-	[FW_ANA_AC_TSN_SF_PORT_NUM] = 7,
-	[FW_ANA_AC_TSN_SF_CFG_TSN_SGID] = 8,
-	[FW_ANA_AC_TSN_SF_STATUS_TSN_SFID] = 8,
-	[FW_ANA_AC_SG_ACCESS_CTRL_SGID] = 8,
-	[FW_ANA_AC_PORT_SGE_CFG_MASK] = 17,
-	[FW_ANA_AC_SDLB_XLB_START_LBSET_START] = 9,
-	[FW_ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT] = 3,
-	[FW_ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT] = 9,
-	[FW_ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT] = 9,
-	[FW_ANA_AC_SDLB_XLB_NEXT_LBGRP] = 3,
-	[FW_ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR] = 9,
-	[FW_ANA_L2_AUTO_LRN_CFG_AUTO_LRN_ENA] = 30,
-	[FW_ANA_L2_DLB_CFG_DLB_IDX] = 9,
-	[FW_ANA_L2_TSN_CFG_TSN_SFID] = 8,
-	[FW_ANA_L3_VLAN_MASK_CFG_VLAN_PORT_MASK] = 30,
-	[FW_FDMA_CH_CFG_CH_DCB_DB_CNT] = 2,
-	[FW_GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL] = 7,
-	[FW_HSCH_SE_CFG_SE_DWRR_CNT] = 5,
-	[FW_HSCH_SE_CONNECT_SE_LEAK_LINK] = 14,
-	[FW_HSCH_SE_DLB_SENSE_SE_DLB_DPORT] = 6,
-	[FW_HSCH_HSCH_CFG_CFG_CFG_SE_IDX] = 11,
-	[FW_HSCH_HSCH_LEAK_CFG_LEAK_FIRST] = 14,
-	[FW_HSCH_FLUSH_CTRL_FLUSH_PORT] = 6,
-	[FW_HSCH_FLUSH_CTRL_FLUSH_HIER] = 14,
-	[FW_LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW] = 13,
-	[FW_LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX] = 8,
-	[FW_LRN_AUTOAGE_CFG_2_NEXT_ROW] = 13,
-	[FW_PTP_PTP_PIN_INTR_INTR_PTP] = 8,
-	[FW_PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA] = 8,
-	[FW_PTP_PTP_INTR_IDENT_INTR_PTP_IDENT] = 8,
-	[FW_PTP_PTP_PIN_CFG_PTP_PIN_SELECT] = 3,
-	[FW_QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL] = 6,
-	[FW_QRES_RES_CFG_WM_HIGH] = 11,
-	[FW_QRES_RES_STAT_MAXUSE] = 19,
-	[FW_QRES_RES_STAT_CUR_INUSE] = 19,
-	[FW_QSYS_PAUSE_CFG_PAUSE_START] = 11,
-	[FW_QSYS_PAUSE_CFG_PAUSE_STOP] = 11,
-	[FW_QSYS_ATOP_ATOP] = 11,
-	[FW_QSYS_ATOP_TOT_CFG_ATOP_TOT] = 11,
-	[FW_REW_RTAG_ETAG_CTRL_IPE_TBL] = 6,
-	[FW_XQS_STAT_CFG_STAT_VIEW] = 10,
-	[FW_XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP] = 14,
-	[FW_XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP] = 14,
-	[FW_XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP] = 14,
-	[FW_XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM] = 14,
-};
--- a/drivers/net/ethernet/microchip/lan969x/lan969x_vcap_ag_api.c
+++ /dev/null
@@ -1,3843 +0,0 @@
-// SPDX-License-Identifier: BSD-3-Clause
-/* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries.
- * Microchip VCAP API
- */
-
-/* This file is autogenerated by cml-utils 2024-10-07 11:10:56 +0200.
- * Commit ID: b5ddc8e244eb2481a9524f1ddc630a8b41e7c391
- */
-
-#include <linux/types.h>
-#include <linux/kernel.h>
-
-#include "lan969x.h"
-
-/* keyfields */
-static const struct vcap_field is0_normal_7tuple_keyfield[] = {
-	[VCAP_KF_TYPE] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 0,
-		.width = 1,
-	},
-	[VCAP_KF_LOOKUP_FIRST_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 1,
-		.width = 1,
-	},
-	[VCAP_KF_LOOKUP_GEN_IDX_SEL] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 2,
-		.width = 2,
-	},
-	[VCAP_KF_LOOKUP_GEN_IDX] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 4,
-		.width = 10,
-	},
-	[VCAP_KF_IF_IGR_PORT_MASK_SEL] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 14,
-		.width = 2,
-	},
-	[VCAP_KF_IF_IGR_PORT_MASK] = {
-		.type = VCAP_FIELD_U72,
-		.offset = 16,
-		.width = 65,
-	},
-	[VCAP_KF_L2_MC_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 81,
-		.width = 1,
-	},
-	[VCAP_KF_L2_BC_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 82,
-		.width = 1,
-	},
-	[VCAP_KF_8021Q_VLAN_TAGS] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 83,
-		.width = 3,
-	},
-	[VCAP_KF_8021Q_TPID0] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 86,
-		.width = 3,
-	},
-	[VCAP_KF_8021Q_PCP0] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 89,
-		.width = 3,
-	},
-	[VCAP_KF_8021Q_DEI0] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 92,
-		.width = 1,
-	},
-	[VCAP_KF_8021Q_VID0] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 93,
-		.width = 12,
-	},
-	[VCAP_KF_8021Q_TPID1] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 105,
-		.width = 3,
-	},
-	[VCAP_KF_8021Q_PCP1] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 108,
-		.width = 3,
-	},
-	[VCAP_KF_8021Q_DEI1] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 111,
-		.width = 1,
-	},
-	[VCAP_KF_8021Q_VID1] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 112,
-		.width = 12,
-	},
-	[VCAP_KF_8021Q_TPID2] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 124,
-		.width = 3,
-	},
-	[VCAP_KF_8021Q_PCP2] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 127,
-		.width = 3,
-	},
-	[VCAP_KF_8021Q_DEI2] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 130,
-		.width = 1,
-	},
-	[VCAP_KF_8021Q_VID2] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 131,
-		.width = 12,
-	},
-	[VCAP_KF_L2_DMAC] = {
-		.type = VCAP_FIELD_U48,
-		.offset = 144,
-		.width = 48,
-	},
-	[VCAP_KF_L2_SMAC] = {
-		.type = VCAP_FIELD_U48,
-		.offset = 192,
-		.width = 48,
-	},
-	[VCAP_KF_IP_MC_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 240,
-		.width = 1,
-	},
-	[VCAP_KF_ETYPE_LEN_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 241,
-		.width = 1,
-	},
-	[VCAP_KF_ETYPE] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 242,
-		.width = 16,
-	},
-	[VCAP_KF_IP_SNAP_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 258,
-		.width = 1,
-	},
-	[VCAP_KF_IP4_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 259,
-		.width = 1,
-	},
-	[VCAP_KF_L3_FRAGMENT_TYPE] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 260,
-		.width = 2,
-	},
-	[VCAP_KF_L3_FRAG_INVLD_L4_LEN] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 262,
-		.width = 1,
-	},
-	[VCAP_KF_L3_OPTIONS_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 263,
-		.width = 1,
-	},
-	[VCAP_KF_L3_DSCP] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 264,
-		.width = 6,
-	},
-	[VCAP_KF_L3_IP6_DIP] = {
-		.type = VCAP_FIELD_U128,
-		.offset = 270,
-		.width = 128,
-	},
-	[VCAP_KF_L3_IP6_SIP] = {
-		.type = VCAP_FIELD_U128,
-		.offset = 398,
-		.width = 128,
-	},
-	[VCAP_KF_TCP_UDP_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 526,
-		.width = 1,
-	},
-	[VCAP_KF_TCP_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 527,
-		.width = 1,
-	},
-	[VCAP_KF_L4_SPORT] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 528,
-		.width = 16,
-	},
-	[VCAP_KF_L4_RNG] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 544,
-		.width = 8,
-	},
-};
-
-static const struct vcap_field is0_normal_5tuple_ip4_keyfield[] = {
-	[VCAP_KF_TYPE] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 0,
-		.width = 2,
-	},
-	[VCAP_KF_LOOKUP_FIRST_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 2,
-		.width = 1,
-	},
-	[VCAP_KF_LOOKUP_GEN_IDX_SEL] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 3,
-		.width = 2,
-	},
-	[VCAP_KF_LOOKUP_GEN_IDX] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 5,
-		.width = 10,
-	},
-	[VCAP_KF_IF_IGR_PORT_MASK_SEL] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 15,
-		.width = 2,
-	},
-	[VCAP_KF_IF_IGR_PORT_MASK] = {
-		.type = VCAP_FIELD_U72,
-		.offset = 17,
-		.width = 65,
-	},
-	[VCAP_KF_L2_MC_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 82,
-		.width = 1,
-	},
-	[VCAP_KF_L2_BC_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 83,
-		.width = 1,
-	},
-	[VCAP_KF_8021Q_VLAN_TAGS] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 84,
-		.width = 3,
-	},
-	[VCAP_KF_8021Q_TPID0] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 87,
-		.width = 3,
-	},
-	[VCAP_KF_8021Q_PCP0] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 90,
-		.width = 3,
-	},
-	[VCAP_KF_8021Q_DEI0] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 93,
-		.width = 1,
-	},
-	[VCAP_KF_8021Q_VID0] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 94,
-		.width = 12,
-	},
-	[VCAP_KF_8021Q_TPID1] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 106,
-		.width = 3,
-	},
-	[VCAP_KF_8021Q_PCP1] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 109,
-		.width = 3,
-	},
-	[VCAP_KF_8021Q_DEI1] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 112,
-		.width = 1,
-	},
-	[VCAP_KF_8021Q_VID1] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 113,
-		.width = 12,
-	},
-	[VCAP_KF_8021Q_TPID2] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 125,
-		.width = 3,
-	},
-	[VCAP_KF_8021Q_PCP2] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 128,
-		.width = 3,
-	},
-	[VCAP_KF_8021Q_DEI2] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 131,
-		.width = 1,
-	},
-	[VCAP_KF_8021Q_VID2] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 132,
-		.width = 12,
-	},
-	[VCAP_KF_IP_MC_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 145,
-		.width = 1,
-	},
-	[VCAP_KF_IP4_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 146,
-		.width = 1,
-	},
-	[VCAP_KF_L3_FRAGMENT_TYPE] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 147,
-		.width = 2,
-	},
-	[VCAP_KF_L3_FRAG_INVLD_L4_LEN] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 149,
-		.width = 1,
-	},
-	[VCAP_KF_L3_OPTIONS_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 150,
-		.width = 1,
-	},
-	[VCAP_KF_L3_DSCP] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 151,
-		.width = 6,
-	},
-	[VCAP_KF_L3_IP4_DIP] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 157,
-		.width = 32,
-	},
-	[VCAP_KF_L3_IP4_SIP] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 189,
-		.width = 32,
-	},
-	[VCAP_KF_L3_IP_PROTO] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 221,
-		.width = 8,
-	},
-	[VCAP_KF_TCP_UDP_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 229,
-		.width = 1,
-	},
-	[VCAP_KF_TCP_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 230,
-		.width = 1,
-	},
-	[VCAP_KF_L4_RNG] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 231,
-		.width = 8,
-	},
-	[VCAP_KF_IP_PAYLOAD_5TUPLE] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 239,
-		.width = 32,
-	},
-};
-
-static const struct vcap_field is2_mac_etype_keyfield[] = {
-	[VCAP_KF_TYPE] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 0,
-		.width = 4,
-	},
-	[VCAP_KF_LOOKUP_FIRST_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 4,
-		.width = 1,
-	},
-	[VCAP_KF_LOOKUP_PAG] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 5,
-		.width = 8,
-	},
-	[VCAP_KF_IF_IGR_PORT_MASK_L3] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 13,
-		.width = 1,
-	},
-	[VCAP_KF_IF_IGR_PORT_MASK_RNG] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 14,
-		.width = 4,
-	},
-	[VCAP_KF_IF_IGR_PORT_MASK_SEL] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 18,
-		.width = 2,
-	},
-	[VCAP_KF_IF_IGR_PORT_MASK] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 20,
-		.width = 32,
-	},
-	[VCAP_KF_L2_MC_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 52,
-		.width = 1,
-	},
-	[VCAP_KF_L2_BC_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 53,
-		.width = 1,
-	},
-	[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 54,
-		.width = 1,
-	},
-	[VCAP_KF_ISDX_GT0_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 56,
-		.width = 1,
-	},
-	[VCAP_KF_ISDX_CLS] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 57,
-		.width = 10,
-	},
-	[VCAP_KF_8021Q_VID_CLS] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 67,
-		.width = 13,
-	},
-	[VCAP_KF_8021Q_DEI_CLS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 80,
-		.width = 1,
-	},
-	[VCAP_KF_8021Q_PCP_CLS] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 81,
-		.width = 3,
-	},
-	[VCAP_KF_L2_FWD_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 84,
-		.width = 1,
-	},
-	[VCAP_KF_L3_RT_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 87,
-		.width = 1,
-	},
-	[VCAP_KF_L3_DST_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 88,
-		.width = 1,
-	},
-	[VCAP_KF_L2_DMAC] = {
-		.type = VCAP_FIELD_U48,
-		.offset = 89,
-		.width = 48,
-	},
-	[VCAP_KF_L2_SMAC] = {
-		.type = VCAP_FIELD_U48,
-		.offset = 137,
-		.width = 48,
-	},
-	[VCAP_KF_ETYPE_LEN_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 185,
-		.width = 1,
-	},
-	[VCAP_KF_ETYPE] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 186,
-		.width = 16,
-	},
-	[VCAP_KF_L2_PAYLOAD_ETYPE] = {
-		.type = VCAP_FIELD_U64,
-		.offset = 202,
-		.width = 64,
-	},
-	[VCAP_KF_L4_RNG] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 266,
-		.width = 16,
-	},
-	[VCAP_KF_OAM_CCM_CNTS_EQ0] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 282,
-		.width = 1,
-	},
-	[VCAP_KF_OAM_Y1731_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 283,
-		.width = 1,
-	},
-};
-
-static const struct vcap_field is2_arp_keyfield[] = {
-	[VCAP_KF_TYPE] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 0,
-		.width = 4,
-	},
-	[VCAP_KF_LOOKUP_FIRST_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 4,
-		.width = 1,
-	},
-	[VCAP_KF_LOOKUP_PAG] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 5,
-		.width = 8,
-	},
-	[VCAP_KF_IF_IGR_PORT_MASK_L3] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 13,
-		.width = 1,
-	},
-	[VCAP_KF_IF_IGR_PORT_MASK_RNG] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 14,
-		.width = 4,
-	},
-	[VCAP_KF_IF_IGR_PORT_MASK_SEL] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 18,
-		.width = 2,
-	},
-	[VCAP_KF_IF_IGR_PORT_MASK] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 20,
-		.width = 32,
-	},
-	[VCAP_KF_L2_MC_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 52,
-		.width = 1,
-	},
-	[VCAP_KF_L2_BC_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 53,
-		.width = 1,
-	},
-	[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 54,
-		.width = 1,
-	},
-	[VCAP_KF_ISDX_GT0_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 56,
-		.width = 1,
-	},
-	[VCAP_KF_ISDX_CLS] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 57,
-		.width = 10,
-	},
-	[VCAP_KF_8021Q_VID_CLS] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 67,
-		.width = 13,
-	},
-	[VCAP_KF_8021Q_DEI_CLS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 80,
-		.width = 1,
-	},
-	[VCAP_KF_8021Q_PCP_CLS] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 81,
-		.width = 3,
-	},
-	[VCAP_KF_L2_FWD_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 84,
-		.width = 1,
-	},
-	[VCAP_KF_L2_SMAC] = {
-		.type = VCAP_FIELD_U48,
-		.offset = 85,
-		.width = 48,
-	},
-	[VCAP_KF_ARP_ADDR_SPACE_OK_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 133,
-		.width = 1,
-	},
-	[VCAP_KF_ARP_PROTO_SPACE_OK_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 134,
-		.width = 1,
-	},
-	[VCAP_KF_ARP_LEN_OK_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 135,
-		.width = 1,
-	},
-	[VCAP_KF_ARP_TGT_MATCH_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 136,
-		.width = 1,
-	},
-	[VCAP_KF_ARP_SENDER_MATCH_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 137,
-		.width = 1,
-	},
-	[VCAP_KF_ARP_OPCODE_UNKNOWN_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 138,
-		.width = 1,
-	},
-	[VCAP_KF_ARP_OPCODE] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 139,
-		.width = 2,
-	},
-	[VCAP_KF_L3_IP4_DIP] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 141,
-		.width = 32,
-	},
-	[VCAP_KF_L3_IP4_SIP] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 173,
-		.width = 32,
-	},
-	[VCAP_KF_L3_DIP_EQ_SIP_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 205,
-		.width = 1,
-	},
-	[VCAP_KF_L4_RNG] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 206,
-		.width = 16,
-	},
-};
-
-static const struct vcap_field is2_ip4_tcp_udp_keyfield[] = {
-	[VCAP_KF_TYPE] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 0,
-		.width = 4,
-	},
-	[VCAP_KF_LOOKUP_FIRST_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 4,
-		.width = 1,
-	},
-	[VCAP_KF_LOOKUP_PAG] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 5,
-		.width = 8,
-	},
-	[VCAP_KF_IF_IGR_PORT_MASK_L3] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 13,
-		.width = 1,
-	},
-	[VCAP_KF_IF_IGR_PORT_MASK_RNG] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 14,
-		.width = 4,
-	},
-	[VCAP_KF_IF_IGR_PORT_MASK_SEL] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 18,
-		.width = 2,
-	},
-	[VCAP_KF_IF_IGR_PORT_MASK] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 20,
-		.width = 32,
-	},
-	[VCAP_KF_L2_MC_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 52,
-		.width = 1,
-	},
-	[VCAP_KF_L2_BC_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 53,
-		.width = 1,
-	},
-	[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 54,
-		.width = 1,
-	},
-	[VCAP_KF_ISDX_GT0_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 56,
-		.width = 1,
-	},
-	[VCAP_KF_ISDX_CLS] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 57,
-		.width = 10,
-	},
-	[VCAP_KF_8021Q_VID_CLS] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 67,
-		.width = 13,
-	},
-	[VCAP_KF_8021Q_DEI_CLS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 80,
-		.width = 1,
-	},
-	[VCAP_KF_8021Q_PCP_CLS] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 81,
-		.width = 3,
-	},
-	[VCAP_KF_L2_FWD_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 84,
-		.width = 1,
-	},
-	[VCAP_KF_L3_RT_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 87,
-		.width = 1,
-	},
-	[VCAP_KF_L3_DST_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 88,
-		.width = 1,
-	},
-	[VCAP_KF_IP4_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 89,
-		.width = 1,
-	},
-	[VCAP_KF_L3_FRAGMENT_TYPE] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 90,
-		.width = 2,
-	},
-	[VCAP_KF_L3_FRAG_INVLD_L4_LEN] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 92,
-		.width = 1,
-	},
-	[VCAP_KF_L3_OPTIONS_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 93,
-		.width = 1,
-	},
-	[VCAP_KF_L3_TTL_GT0] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 94,
-		.width = 1,
-	},
-	[VCAP_KF_L3_TOS] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 95,
-		.width = 8,
-	},
-	[VCAP_KF_L3_IP4_DIP] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 103,
-		.width = 32,
-	},
-	[VCAP_KF_L3_IP4_SIP] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 135,
-		.width = 32,
-	},
-	[VCAP_KF_L3_DIP_EQ_SIP_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 167,
-		.width = 1,
-	},
-	[VCAP_KF_TCP_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 168,
-		.width = 1,
-	},
-	[VCAP_KF_L4_DPORT] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 169,
-		.width = 16,
-	},
-	[VCAP_KF_L4_SPORT] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 185,
-		.width = 16,
-	},
-	[VCAP_KF_L4_RNG] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 201,
-		.width = 16,
-	},
-	[VCAP_KF_L4_SPORT_EQ_DPORT_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 217,
-		.width = 1,
-	},
-	[VCAP_KF_L4_SEQUENCE_EQ0_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 218,
-		.width = 1,
-	},
-	[VCAP_KF_L4_FIN] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 219,
-		.width = 1,
-	},
-	[VCAP_KF_L4_SYN] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 220,
-		.width = 1,
-	},
-	[VCAP_KF_L4_RST] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 221,
-		.width = 1,
-	},
-	[VCAP_KF_L4_PSH] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 222,
-		.width = 1,
-	},
-	[VCAP_KF_L4_ACK] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 223,
-		.width = 1,
-	},
-	[VCAP_KF_L4_URG] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 224,
-		.width = 1,
-	},
-	[VCAP_KF_L4_PAYLOAD] = {
-		.type = VCAP_FIELD_U64,
-		.offset = 225,
-		.width = 64,
-	},
-};
-
-static const struct vcap_field is2_ip4_other_keyfield[] = {
-	[VCAP_KF_TYPE] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 0,
-		.width = 4,
-	},
-	[VCAP_KF_LOOKUP_FIRST_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 4,
-		.width = 1,
-	},
-	[VCAP_KF_LOOKUP_PAG] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 5,
-		.width = 8,
-	},
-	[VCAP_KF_IF_IGR_PORT_MASK_L3] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 13,
-		.width = 1,
-	},
-	[VCAP_KF_IF_IGR_PORT_MASK_RNG] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 14,
-		.width = 4,
-	},
-	[VCAP_KF_IF_IGR_PORT_MASK_SEL] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 18,
-		.width = 2,
-	},
-	[VCAP_KF_IF_IGR_PORT_MASK] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 20,
-		.width = 32,
-	},
-	[VCAP_KF_L2_MC_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 52,
-		.width = 1,
-	},
-	[VCAP_KF_L2_BC_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 53,
-		.width = 1,
-	},
-	[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 54,
-		.width = 1,
-	},
-	[VCAP_KF_ISDX_GT0_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 56,
-		.width = 1,
-	},
-	[VCAP_KF_ISDX_CLS] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 57,
-		.width = 10,
-	},
-	[VCAP_KF_8021Q_VID_CLS] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 67,
-		.width = 13,
-	},
-	[VCAP_KF_8021Q_DEI_CLS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 80,
-		.width = 1,
-	},
-	[VCAP_KF_8021Q_PCP_CLS] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 81,
-		.width = 3,
-	},
-	[VCAP_KF_L2_FWD_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 84,
-		.width = 1,
-	},
-	[VCAP_KF_L3_RT_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 87,
-		.width = 1,
-	},
-	[VCAP_KF_L3_DST_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 88,
-		.width = 1,
-	},
-	[VCAP_KF_IP4_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 89,
-		.width = 1,
-	},
-	[VCAP_KF_L3_FRAGMENT_TYPE] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 90,
-		.width = 2,
-	},
-	[VCAP_KF_L3_FRAG_INVLD_L4_LEN] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 92,
-		.width = 1,
-	},
-	[VCAP_KF_L3_OPTIONS_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 93,
-		.width = 1,
-	},
-	[VCAP_KF_L3_TTL_GT0] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 94,
-		.width = 1,
-	},
-	[VCAP_KF_L3_TOS] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 95,
-		.width = 8,
-	},
-	[VCAP_KF_L3_IP4_DIP] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 103,
-		.width = 32,
-	},
-	[VCAP_KF_L3_IP4_SIP] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 135,
-		.width = 32,
-	},
-	[VCAP_KF_L3_DIP_EQ_SIP_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 167,
-		.width = 1,
-	},
-	[VCAP_KF_L3_IP_PROTO] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 168,
-		.width = 8,
-	},
-	[VCAP_KF_L4_RNG] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 176,
-		.width = 16,
-	},
-	[VCAP_KF_L3_PAYLOAD] = {
-		.type = VCAP_FIELD_U112,
-		.offset = 192,
-		.width = 96,
-	},
-};
-
-static const struct vcap_field is2_ip6_std_keyfield[] = {
-	[VCAP_KF_TYPE] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 0,
-		.width = 4,
-	},
-	[VCAP_KF_LOOKUP_FIRST_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 4,
-		.width = 1,
-	},
-	[VCAP_KF_LOOKUP_PAG] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 5,
-		.width = 8,
-	},
-	[VCAP_KF_IF_IGR_PORT_MASK_L3] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 13,
-		.width = 1,
-	},
-	[VCAP_KF_IF_IGR_PORT_MASK_RNG] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 14,
-		.width = 4,
-	},
-	[VCAP_KF_IF_IGR_PORT_MASK_SEL] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 18,
-		.width = 2,
-	},
-	[VCAP_KF_IF_IGR_PORT_MASK] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 20,
-		.width = 32,
-	},
-	[VCAP_KF_L2_MC_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 52,
-		.width = 1,
-	},
-	[VCAP_KF_L2_BC_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 53,
-		.width = 1,
-	},
-	[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 54,
-		.width = 1,
-	},
-	[VCAP_KF_ISDX_GT0_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 56,
-		.width = 1,
-	},
-	[VCAP_KF_ISDX_CLS] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 57,
-		.width = 10,
-	},
-	[VCAP_KF_8021Q_VID_CLS] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 67,
-		.width = 13,
-	},
-	[VCAP_KF_8021Q_DEI_CLS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 80,
-		.width = 1,
-	},
-	[VCAP_KF_8021Q_PCP_CLS] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 81,
-		.width = 3,
-	},
-	[VCAP_KF_L2_FWD_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 84,
-		.width = 1,
-	},
-	[VCAP_KF_L3_RT_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 87,
-		.width = 1,
-	},
-	[VCAP_KF_L3_TTL_GT0] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 89,
-		.width = 1,
-	},
-	[VCAP_KF_L3_IP6_SIP] = {
-		.type = VCAP_FIELD_U128,
-		.offset = 90,
-		.width = 128,
-	},
-	[VCAP_KF_L3_DIP_EQ_SIP_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 218,
-		.width = 1,
-	},
-	[VCAP_KF_L3_IP_PROTO] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 219,
-		.width = 8,
-	},
-	[VCAP_KF_L4_RNG] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 227,
-		.width = 16,
-	},
-	[VCAP_KF_L3_PAYLOAD] = {
-		.type = VCAP_FIELD_U48,
-		.offset = 243,
-		.width = 40,
-	},
-};
-
-static const struct vcap_field is2_ip_7tuple_keyfield[] = {
-	[VCAP_KF_TYPE] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 0,
-		.width = 2,
-	},
-	[VCAP_KF_LOOKUP_FIRST_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 2,
-		.width = 1,
-	},
-	[VCAP_KF_LOOKUP_PAG] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 3,
-		.width = 8,
-	},
-	[VCAP_KF_IF_IGR_PORT_MASK_L3] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 11,
-		.width = 1,
-	},
-	[VCAP_KF_IF_IGR_PORT_MASK_RNG] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 12,
-		.width = 4,
-	},
-	[VCAP_KF_IF_IGR_PORT_MASK_SEL] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 16,
-		.width = 2,
-	},
-	[VCAP_KF_IF_IGR_PORT_MASK] = {
-		.type = VCAP_FIELD_U72,
-		.offset = 18,
-		.width = 65,
-	},
-	[VCAP_KF_L2_MC_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 83,
-		.width = 1,
-	},
-	[VCAP_KF_L2_BC_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 84,
-		.width = 1,
-	},
-	[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 85,
-		.width = 1,
-	},
-	[VCAP_KF_ISDX_GT0_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 87,
-		.width = 1,
-	},
-	[VCAP_KF_ISDX_CLS] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 88,
-		.width = 10,
-	},
-	[VCAP_KF_8021Q_VID_CLS] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 98,
-		.width = 13,
-	},
-	[VCAP_KF_8021Q_DEI_CLS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 111,
-		.width = 1,
-	},
-	[VCAP_KF_8021Q_PCP_CLS] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 112,
-		.width = 3,
-	},
-	[VCAP_KF_L2_FWD_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 115,
-		.width = 1,
-	},
-	[VCAP_KF_L3_RT_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 118,
-		.width = 1,
-	},
-	[VCAP_KF_L3_DST_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 119,
-		.width = 1,
-	},
-	[VCAP_KF_L2_DMAC] = {
-		.type = VCAP_FIELD_U48,
-		.offset = 120,
-		.width = 48,
-	},
-	[VCAP_KF_L2_SMAC] = {
-		.type = VCAP_FIELD_U48,
-		.offset = 168,
-		.width = 48,
-	},
-	[VCAP_KF_IP4_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 218,
-		.width = 1,
-	},
-	[VCAP_KF_L3_TTL_GT0] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 219,
-		.width = 1,
-	},
-	[VCAP_KF_L3_TOS] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 220,
-		.width = 8,
-	},
-	[VCAP_KF_L3_IP6_DIP] = {
-		.type = VCAP_FIELD_U128,
-		.offset = 228,
-		.width = 128,
-	},
-	[VCAP_KF_L3_IP6_SIP] = {
-		.type = VCAP_FIELD_U128,
-		.offset = 356,
-		.width = 128,
-	},
-	[VCAP_KF_L3_DIP_EQ_SIP_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 484,
-		.width = 1,
-	},
-	[VCAP_KF_TCP_UDP_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 485,
-		.width = 1,
-	},
-	[VCAP_KF_TCP_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 486,
-		.width = 1,
-	},
-	[VCAP_KF_L4_DPORT] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 487,
-		.width = 16,
-	},
-	[VCAP_KF_L4_SPORT] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 503,
-		.width = 16,
-	},
-	[VCAP_KF_L4_RNG] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 519,
-		.width = 16,
-	},
-	[VCAP_KF_L4_SPORT_EQ_DPORT_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 535,
-		.width = 1,
-	},
-	[VCAP_KF_L4_SEQUENCE_EQ0_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 536,
-		.width = 1,
-	},
-	[VCAP_KF_L4_FIN] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 537,
-		.width = 1,
-	},
-	[VCAP_KF_L4_SYN] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 538,
-		.width = 1,
-	},
-	[VCAP_KF_L4_RST] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 539,
-		.width = 1,
-	},
-	[VCAP_KF_L4_PSH] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 540,
-		.width = 1,
-	},
-	[VCAP_KF_L4_ACK] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 541,
-		.width = 1,
-	},
-	[VCAP_KF_L4_URG] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 542,
-		.width = 1,
-	},
-	[VCAP_KF_L4_PAYLOAD] = {
-		.type = VCAP_FIELD_U64,
-		.offset = 543,
-		.width = 64,
-	},
-};
-
-static const struct vcap_field es0_isdx_keyfield[] = {
-	[VCAP_KF_TYPE] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 0,
-		.width = 1,
-	},
-	[VCAP_KF_IF_EGR_PORT_NO] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 1,
-		.width = 6,
-	},
-	[VCAP_KF_8021Q_VID_CLS] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 7,
-		.width = 13,
-	},
-	[VCAP_KF_COSID_CLS] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 20,
-		.width = 3,
-	},
-	[VCAP_KF_8021Q_TPID] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 23,
-		.width = 3,
-	},
-	[VCAP_KF_L3_DPL_CLS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 26,
-		.width = 1,
-	},
-	[VCAP_KF_ISDX_GT0_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 27,
-		.width = 1,
-	},
-	[VCAP_KF_PROT_ACTIVE] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 28,
-		.width = 1,
-	},
-	[VCAP_KF_ISDX_CLS] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 38,
-		.width = 10,
-	},
-};
-
-static const struct vcap_field es2_mac_etype_keyfield[] = {
-	[VCAP_KF_TYPE] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 0,
-		.width = 3,
-	},
-	[VCAP_KF_LOOKUP_FIRST_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 3,
-		.width = 1,
-	},
-	[VCAP_KF_L2_MC_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 13,
-		.width = 1,
-	},
-	[VCAP_KF_L2_BC_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 14,
-		.width = 1,
-	},
-	[VCAP_KF_ISDX_GT0_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 15,
-		.width = 1,
-	},
-	[VCAP_KF_ISDX_CLS] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 16,
-		.width = 10,
-	},
-	[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 26,
-		.width = 1,
-	},
-	[VCAP_KF_8021Q_VID_CLS] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 28,
-		.width = 13,
-	},
-	[VCAP_KF_IF_EGR_PORT_MASK_RNG] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 41,
-		.width = 3,
-	},
-	[VCAP_KF_IF_EGR_PORT_MASK] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 44,
-		.width = 32,
-	},
-	[VCAP_KF_IF_IGR_PORT_SEL] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 76,
-		.width = 1,
-	},
-	[VCAP_KF_IF_IGR_PORT] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 77,
-		.width = 7,
-	},
-	[VCAP_KF_8021Q_PCP_CLS] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 84,
-		.width = 3,
-	},
-	[VCAP_KF_8021Q_DEI_CLS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 87,
-		.width = 1,
-	},
-	[VCAP_KF_COSID_CLS] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 88,
-		.width = 3,
-	},
-	[VCAP_KF_L3_DPL_CLS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 91,
-		.width = 1,
-	},
-	[VCAP_KF_L3_RT_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 92,
-		.width = 1,
-	},
-	[VCAP_KF_L2_DMAC] = {
-		.type = VCAP_FIELD_U48,
-		.offset = 96,
-		.width = 48,
-	},
-	[VCAP_KF_L2_SMAC] = {
-		.type = VCAP_FIELD_U48,
-		.offset = 144,
-		.width = 48,
-	},
-	[VCAP_KF_ETYPE_LEN_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 192,
-		.width = 1,
-	},
-	[VCAP_KF_ETYPE] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 193,
-		.width = 16,
-	},
-	[VCAP_KF_L2_PAYLOAD_ETYPE] = {
-		.type = VCAP_FIELD_U64,
-		.offset = 209,
-		.width = 64,
-	},
-	[VCAP_KF_OAM_CCM_CNTS_EQ0] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 273,
-		.width = 1,
-	},
-	[VCAP_KF_OAM_Y1731_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 274,
-		.width = 1,
-	},
-};
-
-static const struct vcap_field es2_arp_keyfield[] = {
-	[VCAP_KF_TYPE] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 0,
-		.width = 3,
-	},
-	[VCAP_KF_LOOKUP_FIRST_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 3,
-		.width = 1,
-	},
-	[VCAP_KF_L2_MC_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 13,
-		.width = 1,
-	},
-	[VCAP_KF_L2_BC_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 14,
-		.width = 1,
-	},
-	[VCAP_KF_ISDX_GT0_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 15,
-		.width = 1,
-	},
-	[VCAP_KF_ISDX_CLS] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 16,
-		.width = 10,
-	},
-	[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 26,
-		.width = 1,
-	},
-	[VCAP_KF_8021Q_VID_CLS] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 28,
-		.width = 13,
-	},
-	[VCAP_KF_IF_EGR_PORT_MASK_RNG] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 41,
-		.width = 3,
-	},
-	[VCAP_KF_IF_EGR_PORT_MASK] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 44,
-		.width = 32,
-	},
-	[VCAP_KF_IF_IGR_PORT_SEL] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 76,
-		.width = 1,
-	},
-	[VCAP_KF_IF_IGR_PORT] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 77,
-		.width = 7,
-	},
-	[VCAP_KF_8021Q_PCP_CLS] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 84,
-		.width = 3,
-	},
-	[VCAP_KF_8021Q_DEI_CLS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 87,
-		.width = 1,
-	},
-	[VCAP_KF_COSID_CLS] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 88,
-		.width = 3,
-	},
-	[VCAP_KF_L3_DPL_CLS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 91,
-		.width = 1,
-	},
-	[VCAP_KF_L2_SMAC] = {
-		.type = VCAP_FIELD_U48,
-		.offset = 95,
-		.width = 48,
-	},
-	[VCAP_KF_ARP_ADDR_SPACE_OK_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 143,
-		.width = 1,
-	},
-	[VCAP_KF_ARP_PROTO_SPACE_OK_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 144,
-		.width = 1,
-	},
-	[VCAP_KF_ARP_LEN_OK_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 145,
-		.width = 1,
-	},
-	[VCAP_KF_ARP_TGT_MATCH_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 146,
-		.width = 1,
-	},
-	[VCAP_KF_ARP_SENDER_MATCH_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 147,
-		.width = 1,
-	},
-	[VCAP_KF_ARP_OPCODE_UNKNOWN_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 148,
-		.width = 1,
-	},
-	[VCAP_KF_ARP_OPCODE] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 149,
-		.width = 2,
-	},
-	[VCAP_KF_L3_IP4_DIP] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 151,
-		.width = 32,
-	},
-	[VCAP_KF_L3_IP4_SIP] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 183,
-		.width = 32,
-	},
-	[VCAP_KF_L3_DIP_EQ_SIP_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 215,
-		.width = 1,
-	},
-};
-
-static const struct vcap_field es2_ip4_tcp_udp_keyfield[] = {
-	[VCAP_KF_TYPE] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 0,
-		.width = 3,
-	},
-	[VCAP_KF_LOOKUP_FIRST_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 3,
-		.width = 1,
-	},
-	[VCAP_KF_L2_MC_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 13,
-		.width = 1,
-	},
-	[VCAP_KF_L2_BC_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 14,
-		.width = 1,
-	},
-	[VCAP_KF_ISDX_GT0_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 15,
-		.width = 1,
-	},
-	[VCAP_KF_ISDX_CLS] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 16,
-		.width = 10,
-	},
-	[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 26,
-		.width = 1,
-	},
-	[VCAP_KF_8021Q_VID_CLS] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 28,
-		.width = 13,
-	},
-	[VCAP_KF_IF_EGR_PORT_MASK_RNG] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 41,
-		.width = 3,
-	},
-	[VCAP_KF_IF_EGR_PORT_MASK] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 44,
-		.width = 32,
-	},
-	[VCAP_KF_IF_IGR_PORT_SEL] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 76,
-		.width = 1,
-	},
-	[VCAP_KF_IF_IGR_PORT] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 77,
-		.width = 7,
-	},
-	[VCAP_KF_8021Q_PCP_CLS] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 84,
-		.width = 3,
-	},
-	[VCAP_KF_8021Q_DEI_CLS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 87,
-		.width = 1,
-	},
-	[VCAP_KF_COSID_CLS] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 88,
-		.width = 3,
-	},
-	[VCAP_KF_L3_DPL_CLS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 91,
-		.width = 1,
-	},
-	[VCAP_KF_L3_RT_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 92,
-		.width = 1,
-	},
-	[VCAP_KF_IP4_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 96,
-		.width = 1,
-	},
-	[VCAP_KF_L3_FRAGMENT_TYPE] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 97,
-		.width = 2,
-	},
-	[VCAP_KF_L3_OPTIONS_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 99,
-		.width = 1,
-	},
-	[VCAP_KF_L3_TTL_GT0] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 100,
-		.width = 1,
-	},
-	[VCAP_KF_L3_TOS] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 101,
-		.width = 8,
-	},
-	[VCAP_KF_L3_IP4_DIP] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 109,
-		.width = 32,
-	},
-	[VCAP_KF_L3_IP4_SIP] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 141,
-		.width = 32,
-	},
-	[VCAP_KF_L3_DIP_EQ_SIP_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 173,
-		.width = 1,
-	},
-	[VCAP_KF_TCP_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 174,
-		.width = 1,
-	},
-	[VCAP_KF_L4_DPORT] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 175,
-		.width = 16,
-	},
-	[VCAP_KF_L4_SPORT] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 191,
-		.width = 16,
-	},
-	[VCAP_KF_L4_RNG] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 207,
-		.width = 16,
-	},
-	[VCAP_KF_L4_SPORT_EQ_DPORT_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 223,
-		.width = 1,
-	},
-	[VCAP_KF_L4_SEQUENCE_EQ0_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 224,
-		.width = 1,
-	},
-	[VCAP_KF_L4_FIN] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 225,
-		.width = 1,
-	},
-	[VCAP_KF_L4_SYN] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 226,
-		.width = 1,
-	},
-	[VCAP_KF_L4_RST] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 227,
-		.width = 1,
-	},
-	[VCAP_KF_L4_PSH] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 228,
-		.width = 1,
-	},
-	[VCAP_KF_L4_ACK] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 229,
-		.width = 1,
-	},
-	[VCAP_KF_L4_URG] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 230,
-		.width = 1,
-	},
-	[VCAP_KF_L4_PAYLOAD] = {
-		.type = VCAP_FIELD_U64,
-		.offset = 231,
-		.width = 64,
-	},
-};
-
-static const struct vcap_field es2_ip4_other_keyfield[] = {
-	[VCAP_KF_TYPE] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 0,
-		.width = 3,
-	},
-	[VCAP_KF_LOOKUP_FIRST_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 3,
-		.width = 1,
-	},
-	[VCAP_KF_L2_MC_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 13,
-		.width = 1,
-	},
-	[VCAP_KF_L2_BC_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 14,
-		.width = 1,
-	},
-	[VCAP_KF_ISDX_GT0_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 15,
-		.width = 1,
-	},
-	[VCAP_KF_ISDX_CLS] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 16,
-		.width = 10,
-	},
-	[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 26,
-		.width = 1,
-	},
-	[VCAP_KF_8021Q_VID_CLS] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 28,
-		.width = 13,
-	},
-	[VCAP_KF_IF_EGR_PORT_MASK_RNG] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 41,
-		.width = 3,
-	},
-	[VCAP_KF_IF_EGR_PORT_MASK] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 44,
-		.width = 32,
-	},
-	[VCAP_KF_IF_IGR_PORT_SEL] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 76,
-		.width = 1,
-	},
-	[VCAP_KF_IF_IGR_PORT] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 77,
-		.width = 7,
-	},
-	[VCAP_KF_8021Q_PCP_CLS] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 84,
-		.width = 3,
-	},
-	[VCAP_KF_8021Q_DEI_CLS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 87,
-		.width = 1,
-	},
-	[VCAP_KF_COSID_CLS] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 88,
-		.width = 3,
-	},
-	[VCAP_KF_L3_DPL_CLS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 91,
-		.width = 1,
-	},
-	[VCAP_KF_L3_RT_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 92,
-		.width = 1,
-	},
-	[VCAP_KF_IP4_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 96,
-		.width = 1,
-	},
-	[VCAP_KF_L3_FRAGMENT_TYPE] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 97,
-		.width = 2,
-	},
-	[VCAP_KF_L3_OPTIONS_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 99,
-		.width = 1,
-	},
-	[VCAP_KF_L3_TTL_GT0] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 100,
-		.width = 1,
-	},
-	[VCAP_KF_L3_TOS] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 101,
-		.width = 8,
-	},
-	[VCAP_KF_L3_IP4_DIP] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 109,
-		.width = 32,
-	},
-	[VCAP_KF_L3_IP4_SIP] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 141,
-		.width = 32,
-	},
-	[VCAP_KF_L3_DIP_EQ_SIP_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 173,
-		.width = 1,
-	},
-	[VCAP_KF_L3_IP_PROTO] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 174,
-		.width = 8,
-	},
-	[VCAP_KF_L3_PAYLOAD] = {
-		.type = VCAP_FIELD_U112,
-		.offset = 182,
-		.width = 96,
-	},
-};
-
-static const struct vcap_field es2_ip_7tuple_keyfield[] = {
-	[VCAP_KF_LOOKUP_FIRST_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 0,
-		.width = 1,
-	},
-	[VCAP_KF_L2_MC_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 10,
-		.width = 1,
-	},
-	[VCAP_KF_L2_BC_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 11,
-		.width = 1,
-	},
-	[VCAP_KF_ISDX_GT0_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 12,
-		.width = 1,
-	},
-	[VCAP_KF_ISDX_CLS] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 13,
-		.width = 10,
-	},
-	[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 23,
-		.width = 1,
-	},
-	[VCAP_KF_8021Q_VID_CLS] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 25,
-		.width = 13,
-	},
-	[VCAP_KF_IF_EGR_PORT_MASK_RNG] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 38,
-		.width = 3,
-	},
-	[VCAP_KF_IF_EGR_PORT_MASK] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 41,
-		.width = 32,
-	},
-	[VCAP_KF_IF_IGR_PORT_SEL] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 73,
-		.width = 1,
-	},
-	[VCAP_KF_IF_IGR_PORT] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 74,
-		.width = 7,
-	},
-	[VCAP_KF_8021Q_PCP_CLS] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 81,
-		.width = 3,
-	},
-	[VCAP_KF_8021Q_DEI_CLS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 84,
-		.width = 1,
-	},
-	[VCAP_KF_COSID_CLS] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 85,
-		.width = 3,
-	},
-	[VCAP_KF_L3_DPL_CLS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 88,
-		.width = 1,
-	},
-	[VCAP_KF_L3_RT_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 89,
-		.width = 1,
-	},
-	[VCAP_KF_L2_DMAC] = {
-		.type = VCAP_FIELD_U48,
-		.offset = 93,
-		.width = 48,
-	},
-	[VCAP_KF_L2_SMAC] = {
-		.type = VCAP_FIELD_U48,
-		.offset = 141,
-		.width = 48,
-	},
-	[VCAP_KF_IP4_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 191,
-		.width = 1,
-	},
-	[VCAP_KF_L3_TTL_GT0] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 192,
-		.width = 1,
-	},
-	[VCAP_KF_L3_TOS] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 193,
-		.width = 8,
-	},
-	[VCAP_KF_L3_IP6_DIP] = {
-		.type = VCAP_FIELD_U128,
-		.offset = 201,
-		.width = 128,
-	},
-	[VCAP_KF_L3_IP6_SIP] = {
-		.type = VCAP_FIELD_U128,
-		.offset = 329,
-		.width = 128,
-	},
-	[VCAP_KF_L3_DIP_EQ_SIP_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 457,
-		.width = 1,
-	},
-	[VCAP_KF_TCP_UDP_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 458,
-		.width = 1,
-	},
-	[VCAP_KF_TCP_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 459,
-		.width = 1,
-	},
-	[VCAP_KF_L4_DPORT] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 460,
-		.width = 16,
-	},
-	[VCAP_KF_L4_SPORT] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 476,
-		.width = 16,
-	},
-	[VCAP_KF_L4_RNG] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 492,
-		.width = 16,
-	},
-	[VCAP_KF_L4_SPORT_EQ_DPORT_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 508,
-		.width = 1,
-	},
-	[VCAP_KF_L4_SEQUENCE_EQ0_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 509,
-		.width = 1,
-	},
-	[VCAP_KF_L4_FIN] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 510,
-		.width = 1,
-	},
-	[VCAP_KF_L4_SYN] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 511,
-		.width = 1,
-	},
-	[VCAP_KF_L4_RST] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 512,
-		.width = 1,
-	},
-	[VCAP_KF_L4_PSH] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 513,
-		.width = 1,
-	},
-	[VCAP_KF_L4_ACK] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 514,
-		.width = 1,
-	},
-	[VCAP_KF_L4_URG] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 515,
-		.width = 1,
-	},
-	[VCAP_KF_L4_PAYLOAD] = {
-		.type = VCAP_FIELD_U64,
-		.offset = 516,
-		.width = 64,
-	},
-};
-
-static const struct vcap_field es2_ip6_std_keyfield[] = {
-	[VCAP_KF_TYPE] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 0,
-		.width = 3,
-	},
-	[VCAP_KF_LOOKUP_FIRST_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 3,
-		.width = 1,
-	},
-	[VCAP_KF_L2_MC_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 13,
-		.width = 1,
-	},
-	[VCAP_KF_L2_BC_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 14,
-		.width = 1,
-	},
-	[VCAP_KF_ISDX_GT0_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 15,
-		.width = 1,
-	},
-	[VCAP_KF_ISDX_CLS] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 16,
-		.width = 10,
-	},
-	[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 26,
-		.width = 1,
-	},
-	[VCAP_KF_8021Q_VID_CLS] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 28,
-		.width = 13,
-	},
-	[VCAP_KF_IF_EGR_PORT_MASK_RNG] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 41,
-		.width = 3,
-	},
-	[VCAP_KF_IF_EGR_PORT_MASK] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 44,
-		.width = 32,
-	},
-	[VCAP_KF_IF_IGR_PORT_SEL] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 76,
-		.width = 1,
-	},
-	[VCAP_KF_IF_IGR_PORT] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 77,
-		.width = 7,
-	},
-	[VCAP_KF_8021Q_PCP_CLS] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 84,
-		.width = 3,
-	},
-	[VCAP_KF_8021Q_DEI_CLS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 87,
-		.width = 1,
-	},
-	[VCAP_KF_COSID_CLS] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 88,
-		.width = 3,
-	},
-	[VCAP_KF_L3_DPL_CLS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 91,
-		.width = 1,
-	},
-	[VCAP_KF_L3_RT_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 92,
-		.width = 1,
-	},
-	[VCAP_KF_L3_TTL_GT0] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 96,
-		.width = 1,
-	},
-	[VCAP_KF_L3_IP6_SIP] = {
-		.type = VCAP_FIELD_U128,
-		.offset = 97,
-		.width = 128,
-	},
-	[VCAP_KF_L3_DIP_EQ_SIP_IS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 225,
-		.width = 1,
-	},
-	[VCAP_KF_L3_IP_PROTO] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 226,
-		.width = 8,
-	},
-	[VCAP_KF_L4_RNG] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 234,
-		.width = 16,
-	},
-	[VCAP_KF_L3_PAYLOAD] = {
-		.type = VCAP_FIELD_U48,
-		.offset = 250,
-		.width = 40,
-	},
-};
-
-/* keyfield_set */
-static const struct vcap_set is0_keyfield_set[] = {
-	[VCAP_KFS_NORMAL_7TUPLE] = {
-		.type_id = 0,
-		.sw_per_item = 12,
-		.sw_cnt = 1,
-	},
-	[VCAP_KFS_NORMAL_5TUPLE_IP4] = {
-		.type_id = 2,
-		.sw_per_item = 6,
-		.sw_cnt = 2,
-	},
-};
-
-static const struct vcap_set is2_keyfield_set[] = {
-	[VCAP_KFS_MAC_ETYPE] = {
-		.type_id = 0,
-		.sw_per_item = 6,
-		.sw_cnt = 2,
-	},
-	[VCAP_KFS_ARP] = {
-		.type_id = 3,
-		.sw_per_item = 6,
-		.sw_cnt = 2,
-	},
-	[VCAP_KFS_IP4_TCP_UDP] = {
-		.type_id = 4,
-		.sw_per_item = 6,
-		.sw_cnt = 2,
-	},
-	[VCAP_KFS_IP4_OTHER] = {
-		.type_id = 5,
-		.sw_per_item = 6,
-		.sw_cnt = 2,
-	},
-	[VCAP_KFS_IP6_STD] = {
-		.type_id = 6,
-		.sw_per_item = 6,
-		.sw_cnt = 2,
-	},
-	[VCAP_KFS_IP_7TUPLE] = {
-		.type_id = 1,
-		.sw_per_item = 12,
-		.sw_cnt = 1,
-	},
-};
-
-static const struct vcap_set es0_keyfield_set[] = {
-	[VCAP_KFS_ISDX] = {
-		.type_id = 0,
-		.sw_per_item = 1,
-		.sw_cnt = 1,
-	},
-};
-
-static const struct vcap_set es2_keyfield_set[] = {
-	[VCAP_KFS_MAC_ETYPE] = {
-		.type_id = 0,
-		.sw_per_item = 6,
-		.sw_cnt = 2,
-	},
-	[VCAP_KFS_ARP] = {
-		.type_id = 1,
-		.sw_per_item = 6,
-		.sw_cnt = 2,
-	},
-	[VCAP_KFS_IP4_TCP_UDP] = {
-		.type_id = 2,
-		.sw_per_item = 6,
-		.sw_cnt = 2,
-	},
-	[VCAP_KFS_IP4_OTHER] = {
-		.type_id = 3,
-		.sw_per_item = 6,
-		.sw_cnt = 2,
-	},
-	[VCAP_KFS_IP_7TUPLE] = {
-		.type_id = -1,
-		.sw_per_item = 12,
-		.sw_cnt = 1,
-	},
-	[VCAP_KFS_IP6_STD] = {
-		.type_id = 4,
-		.sw_per_item = 6,
-		.sw_cnt = 2,
-	},
-};
-
-/* keyfield_set map */
-static const struct vcap_field *is0_keyfield_set_map[] = {
-	[VCAP_KFS_NORMAL_7TUPLE] = is0_normal_7tuple_keyfield,
-	[VCAP_KFS_NORMAL_5TUPLE_IP4] = is0_normal_5tuple_ip4_keyfield,
-};
-
-static const struct vcap_field *is2_keyfield_set_map[] = {
-	[VCAP_KFS_MAC_ETYPE] = is2_mac_etype_keyfield,
-	[VCAP_KFS_ARP] = is2_arp_keyfield,
-	[VCAP_KFS_IP4_TCP_UDP] = is2_ip4_tcp_udp_keyfield,
-	[VCAP_KFS_IP4_OTHER] = is2_ip4_other_keyfield,
-	[VCAP_KFS_IP6_STD] = is2_ip6_std_keyfield,
-	[VCAP_KFS_IP_7TUPLE] = is2_ip_7tuple_keyfield,
-};
-
-static const struct vcap_field *es0_keyfield_set_map[] = {
-	[VCAP_KFS_ISDX] = es0_isdx_keyfield,
-};
-
-static const struct vcap_field *es2_keyfield_set_map[] = {
-	[VCAP_KFS_MAC_ETYPE] = es2_mac_etype_keyfield,
-	[VCAP_KFS_ARP] = es2_arp_keyfield,
-	[VCAP_KFS_IP4_TCP_UDP] = es2_ip4_tcp_udp_keyfield,
-	[VCAP_KFS_IP4_OTHER] = es2_ip4_other_keyfield,
-	[VCAP_KFS_IP_7TUPLE] = es2_ip_7tuple_keyfield,
-	[VCAP_KFS_IP6_STD] = es2_ip6_std_keyfield,
-};
-
-/* keyfield_set map sizes */
-static int is0_keyfield_set_map_size[] = {
-	[VCAP_KFS_NORMAL_7TUPLE] = ARRAY_SIZE(is0_normal_7tuple_keyfield),
-	[VCAP_KFS_NORMAL_5TUPLE_IP4] = ARRAY_SIZE(is0_normal_5tuple_ip4_keyfield),
-};
-
-static int is2_keyfield_set_map_size[] = {
-	[VCAP_KFS_MAC_ETYPE] = ARRAY_SIZE(is2_mac_etype_keyfield),
-	[VCAP_KFS_ARP] = ARRAY_SIZE(is2_arp_keyfield),
-	[VCAP_KFS_IP4_TCP_UDP] = ARRAY_SIZE(is2_ip4_tcp_udp_keyfield),
-	[VCAP_KFS_IP4_OTHER] = ARRAY_SIZE(is2_ip4_other_keyfield),
-	[VCAP_KFS_IP6_STD] = ARRAY_SIZE(is2_ip6_std_keyfield),
-	[VCAP_KFS_IP_7TUPLE] = ARRAY_SIZE(is2_ip_7tuple_keyfield),
-};
-
-static int es0_keyfield_set_map_size[] = {
-	[VCAP_KFS_ISDX] = ARRAY_SIZE(es0_isdx_keyfield),
-};
-
-static int es2_keyfield_set_map_size[] = {
-	[VCAP_KFS_MAC_ETYPE] = ARRAY_SIZE(es2_mac_etype_keyfield),
-	[VCAP_KFS_ARP] = ARRAY_SIZE(es2_arp_keyfield),
-	[VCAP_KFS_IP4_TCP_UDP] = ARRAY_SIZE(es2_ip4_tcp_udp_keyfield),
-	[VCAP_KFS_IP4_OTHER] = ARRAY_SIZE(es2_ip4_other_keyfield),
-	[VCAP_KFS_IP_7TUPLE] = ARRAY_SIZE(es2_ip_7tuple_keyfield),
-	[VCAP_KFS_IP6_STD] = ARRAY_SIZE(es2_ip6_std_keyfield),
-};
-
-/* actionfields */
-static const struct vcap_field is0_classification_actionfield[] = {
-	[VCAP_AF_TYPE] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 0,
-		.width = 1,
-	},
-	[VCAP_AF_DSCP_ENA] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 1,
-		.width = 1,
-	},
-	[VCAP_AF_DSCP_VAL] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 2,
-		.width = 6,
-	},
-	[VCAP_AF_QOS_ENA] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 12,
-		.width = 1,
-	},
-	[VCAP_AF_QOS_VAL] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 13,
-		.width = 3,
-	},
-	[VCAP_AF_DP_ENA] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 16,
-		.width = 1,
-	},
-	[VCAP_AF_DP_VAL] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 17,
-		.width = 2,
-	},
-	[VCAP_AF_DEI_ENA] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 19,
-		.width = 1,
-	},
-	[VCAP_AF_DEI_VAL] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 20,
-		.width = 1,
-	},
-	[VCAP_AF_PCP_ENA] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 21,
-		.width = 1,
-	},
-	[VCAP_AF_PCP_VAL] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 22,
-		.width = 3,
-	},
-	[VCAP_AF_MAP_LOOKUP_SEL] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 25,
-		.width = 2,
-	},
-	[VCAP_AF_MAP_KEY] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 27,
-		.width = 3,
-	},
-	[VCAP_AF_MAP_IDX] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 30,
-		.width = 7,
-	},
-	[VCAP_AF_CLS_VID_SEL] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 37,
-		.width = 3,
-	},
-	[VCAP_AF_VID_VAL] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 43,
-		.width = 13,
-	},
-	[VCAP_AF_ISDX_ADD_REPLACE_SEL] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 66,
-		.width = 1,
-	},
-	[VCAP_AF_ISDX_VAL] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 67,
-		.width = 10,
-	},
-	[VCAP_AF_PAG_OVERRIDE_MASK] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 107,
-		.width = 8,
-	},
-	[VCAP_AF_PAG_VAL] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 115,
-		.width = 8,
-	},
-	[VCAP_AF_NXT_IDX_CTRL] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 167,
-		.width = 3,
-	},
-	[VCAP_AF_NXT_IDX] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 170,
-		.width = 10,
-	},
-};
-
-static const struct vcap_field is0_full_actionfield[] = {
-	[VCAP_AF_DSCP_ENA] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 0,
-		.width = 1,
-	},
-	[VCAP_AF_DSCP_VAL] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 1,
-		.width = 6,
-	},
-	[VCAP_AF_QOS_ENA] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 11,
-		.width = 1,
-	},
-	[VCAP_AF_QOS_VAL] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 12,
-		.width = 3,
-	},
-	[VCAP_AF_DP_ENA] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 15,
-		.width = 1,
-	},
-	[VCAP_AF_DP_VAL] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 16,
-		.width = 2,
-	},
-	[VCAP_AF_DEI_ENA] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 18,
-		.width = 1,
-	},
-	[VCAP_AF_DEI_VAL] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 19,
-		.width = 1,
-	},
-	[VCAP_AF_PCP_ENA] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 20,
-		.width = 1,
-	},
-	[VCAP_AF_PCP_VAL] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 21,
-		.width = 3,
-	},
-	[VCAP_AF_MAP_LOOKUP_SEL] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 24,
-		.width = 2,
-	},
-	[VCAP_AF_MAP_KEY] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 26,
-		.width = 3,
-	},
-	[VCAP_AF_MAP_IDX] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 29,
-		.width = 7,
-	},
-	[VCAP_AF_CLS_VID_SEL] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 36,
-		.width = 3,
-	},
-	[VCAP_AF_VID_VAL] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 42,
-		.width = 13,
-	},
-	[VCAP_AF_ISDX_ADD_REPLACE_SEL] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 65,
-		.width = 1,
-	},
-	[VCAP_AF_ISDX_VAL] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 66,
-		.width = 10,
-	},
-	[VCAP_AF_MASK_MODE] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 76,
-		.width = 3,
-	},
-	[VCAP_AF_PORT_MASK] = {
-		.type = VCAP_FIELD_U48,
-		.offset = 79,
-		.width = 37,
-	},
-	[VCAP_AF_PAG_OVERRIDE_MASK] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 174,
-		.width = 8,
-	},
-	[VCAP_AF_PAG_VAL] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 182,
-		.width = 8,
-	},
-	[VCAP_AF_NXT_IDX_CTRL] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 266,
-		.width = 3,
-	},
-	[VCAP_AF_NXT_IDX] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 269,
-		.width = 10,
-	},
-};
-
-static const struct vcap_field is0_class_reduced_actionfield[] = {
-	[VCAP_AF_TYPE] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 0,
-		.width = 1,
-	},
-	[VCAP_AF_QOS_ENA] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 5,
-		.width = 1,
-	},
-	[VCAP_AF_QOS_VAL] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 6,
-		.width = 3,
-	},
-	[VCAP_AF_DP_ENA] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 9,
-		.width = 1,
-	},
-	[VCAP_AF_DP_VAL] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 10,
-		.width = 2,
-	},
-	[VCAP_AF_MAP_LOOKUP_SEL] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 12,
-		.width = 2,
-	},
-	[VCAP_AF_MAP_KEY] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 14,
-		.width = 3,
-	},
-	[VCAP_AF_CLS_VID_SEL] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 17,
-		.width = 3,
-	},
-	[VCAP_AF_VID_VAL] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 23,
-		.width = 13,
-	},
-	[VCAP_AF_ISDX_ADD_REPLACE_SEL] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 46,
-		.width = 1,
-	},
-	[VCAP_AF_ISDX_VAL] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 47,
-		.width = 10,
-	},
-	[VCAP_AF_NXT_IDX_CTRL] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 89,
-		.width = 3,
-	},
-	[VCAP_AF_NXT_IDX] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 92,
-		.width = 10,
-	},
-};
-
-static const struct vcap_field is2_base_type_actionfield[] = {
-	[VCAP_AF_PIPELINE_FORCE_ENA] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 1,
-		.width = 1,
-	},
-	[VCAP_AF_PIPELINE_PT] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 2,
-		.width = 5,
-	},
-	[VCAP_AF_HIT_ME_ONCE] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 7,
-		.width = 1,
-	},
-	[VCAP_AF_INTR_ENA] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 8,
-		.width = 1,
-	},
-	[VCAP_AF_CPU_COPY_ENA] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 9,
-		.width = 1,
-	},
-	[VCAP_AF_CPU_QUEUE_NUM] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 10,
-		.width = 3,
-	},
-	[VCAP_AF_LRN_DIS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 15,
-		.width = 1,
-	},
-	[VCAP_AF_RT_DIS] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 16,
-		.width = 1,
-	},
-	[VCAP_AF_POLICE_ENA] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 17,
-		.width = 1,
-	},
-	[VCAP_AF_POLICE_IDX] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 18,
-		.width = 5,
-	},
-	[VCAP_AF_IGNORE_PIPELINE_CTRL] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 23,
-		.width = 1,
-	},
-	[VCAP_AF_MASK_MODE] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 27,
-		.width = 3,
-	},
-	[VCAP_AF_PORT_MASK] = {
-		.type = VCAP_FIELD_U48,
-		.offset = 30,
-		.width = 37,
-	},
-	[VCAP_AF_MIRROR_PROBE] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 78,
-		.width = 2,
-	},
-	[VCAP_AF_MATCH_ID] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 131,
-		.width = 16,
-	},
-	[VCAP_AF_MATCH_ID_MASK] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 147,
-		.width = 16,
-	},
-	[VCAP_AF_CNT_ID] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 163,
-		.width = 10,
-	},
-};
-
-static const struct vcap_field es0_es0_actionfield[] = {
-	[VCAP_AF_PUSH_OUTER_TAG] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 0,
-		.width = 2,
-	},
-	[VCAP_AF_PUSH_INNER_TAG] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 2,
-		.width = 1,
-	},
-	[VCAP_AF_TAG_A_TPID_SEL] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 3,
-		.width = 3,
-	},
-	[VCAP_AF_TAG_A_VID_SEL] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 6,
-		.width = 2,
-	},
-	[VCAP_AF_TAG_A_PCP_SEL] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 8,
-		.width = 3,
-	},
-	[VCAP_AF_TAG_A_DEI_SEL] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 11,
-		.width = 3,
-	},
-	[VCAP_AF_TAG_B_TPID_SEL] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 14,
-		.width = 3,
-	},
-	[VCAP_AF_TAG_B_VID_SEL] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 17,
-		.width = 2,
-	},
-	[VCAP_AF_TAG_B_PCP_SEL] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 19,
-		.width = 3,
-	},
-	[VCAP_AF_TAG_B_DEI_SEL] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 22,
-		.width = 3,
-	},
-	[VCAP_AF_TAG_C_TPID_SEL] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 25,
-		.width = 3,
-	},
-	[VCAP_AF_TAG_C_PCP_SEL] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 28,
-		.width = 3,
-	},
-	[VCAP_AF_TAG_C_DEI_SEL] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 31,
-		.width = 3,
-	},
-	[VCAP_AF_VID_A_VAL] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 34,
-		.width = 12,
-	},
-	[VCAP_AF_PCP_A_VAL] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 46,
-		.width = 3,
-	},
-	[VCAP_AF_DEI_A_VAL] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 49,
-		.width = 1,
-	},
-	[VCAP_AF_VID_B_VAL] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 50,
-		.width = 12,
-	},
-	[VCAP_AF_PCP_B_VAL] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 62,
-		.width = 3,
-	},
-	[VCAP_AF_DEI_B_VAL] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 65,
-		.width = 1,
-	},
-	[VCAP_AF_VID_C_VAL] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 66,
-		.width = 12,
-	},
-	[VCAP_AF_PCP_C_VAL] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 78,
-		.width = 3,
-	},
-	[VCAP_AF_DEI_C_VAL] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 81,
-		.width = 1,
-	},
-	[VCAP_AF_POP_VAL] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 82,
-		.width = 2,
-	},
-	[VCAP_AF_UNTAG_VID_ENA] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 84,
-		.width = 1,
-	},
-	[VCAP_AF_PUSH_CUSTOMER_TAG] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 85,
-		.width = 2,
-	},
-	[VCAP_AF_TAG_C_VID_SEL] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 87,
-		.width = 2,
-	},
-	[VCAP_AF_DSCP_SEL] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 127,
-		.width = 3,
-	},
-	[VCAP_AF_DSCP_VAL] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 130,
-		.width = 6,
-	},
-	[VCAP_AF_ESDX] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 319,
-		.width = 10,
-	},
-	[VCAP_AF_FWD_SEL] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 438,
-		.width = 2,
-	},
-	[VCAP_AF_CPU_QU] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 440,
-		.width = 3,
-	},
-	[VCAP_AF_PIPELINE_PT] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 443,
-		.width = 2,
-	},
-	[VCAP_AF_PIPELINE_ACT] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 445,
-		.width = 1,
-	},
-	[VCAP_AF_SWAP_MACS_ENA] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 454,
-		.width = 1,
-	},
-	[VCAP_AF_LOOP_ENA] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 455,
-		.width = 1,
-	},
-};
-
-static const struct vcap_field es2_base_type_actionfield[] = {
-	[VCAP_AF_HIT_ME_ONCE] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 0,
-		.width = 1,
-	},
-	[VCAP_AF_INTR_ENA] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 1,
-		.width = 1,
-	},
-	[VCAP_AF_FWD_MODE] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 2,
-		.width = 2,
-	},
-	[VCAP_AF_COPY_QUEUE_NUM] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 4,
-		.width = 14,
-	},
-	[VCAP_AF_COPY_PORT_NUM] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 18,
-		.width = 6,
-	},
-	[VCAP_AF_MIRROR_PROBE_ID] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 24,
-		.width = 2,
-	},
-	[VCAP_AF_CPU_COPY_ENA] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 26,
-		.width = 1,
-	},
-	[VCAP_AF_CPU_QUEUE_NUM] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 27,
-		.width = 3,
-	},
-	[VCAP_AF_POLICE_ENA] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 30,
-		.width = 1,
-	},
-	[VCAP_AF_POLICE_REMARK] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 31,
-		.width = 1,
-	},
-	[VCAP_AF_POLICE_IDX] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 32,
-		.width = 5,
-	},
-	[VCAP_AF_ES2_REW_CMD] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 37,
-		.width = 3,
-	},
-	[VCAP_AF_CNT_ID] = {
-		.type = VCAP_FIELD_U32,
-		.offset = 40,
-		.width = 9,
-	},
-	[VCAP_AF_IGNORE_PIPELINE_CTRL] = {
-		.type = VCAP_FIELD_BIT,
-		.offset = 49,
-		.width = 1,
-	},
-};
-
-/* actionfield_set */
-static const struct vcap_set is0_actionfield_set[] = {
-	[VCAP_AFS_CLASSIFICATION] = {
-		.type_id = 1,
-		.sw_per_item = 2,
-		.sw_cnt = 6,
-	},
-	[VCAP_AFS_FULL] = {
-		.type_id = -1,
-		.sw_per_item = 3,
-		.sw_cnt = 4,
-	},
-	[VCAP_AFS_CLASS_REDUCED] = {
-		.type_id = 1,
-		.sw_per_item = 1,
-		.sw_cnt = 12,
-	},
-};
-
-static const struct vcap_set is2_actionfield_set[] = {
-	[VCAP_AFS_BASE_TYPE] = {
-		.type_id = -1,
-		.sw_per_item = 3,
-		.sw_cnt = 4,
-	},
-};
-
-static const struct vcap_set es0_actionfield_set[] = {
-	[VCAP_AFS_ES0] = {
-		.type_id = -1,
-		.sw_per_item = 1,
-		.sw_cnt = 1,
-	},
-};
-
-static const struct vcap_set es2_actionfield_set[] = {
-	[VCAP_AFS_BASE_TYPE] = {
-		.type_id = -1,
-		.sw_per_item = 3,
-		.sw_cnt = 4,
-	},
-};
-
-/* actionfield_set map */
-static const struct vcap_field *is0_actionfield_set_map[] = {
-	[VCAP_AFS_CLASSIFICATION] = is0_classification_actionfield,
-	[VCAP_AFS_FULL] = is0_full_actionfield,
-	[VCAP_AFS_CLASS_REDUCED] = is0_class_reduced_actionfield,
-};
-
-static const struct vcap_field *is2_actionfield_set_map[] = {
-	[VCAP_AFS_BASE_TYPE] = is2_base_type_actionfield,
-};
-
-static const struct vcap_field *es0_actionfield_set_map[] = {
-	[VCAP_AFS_ES0] = es0_es0_actionfield,
-};
-
-static const struct vcap_field *es2_actionfield_set_map[] = {
-	[VCAP_AFS_BASE_TYPE] = es2_base_type_actionfield,
-};
-
-/* actionfield_set map size */
-static int is0_actionfield_set_map_size[] = {
-	[VCAP_AFS_CLASSIFICATION] = ARRAY_SIZE(is0_classification_actionfield),
-	[VCAP_AFS_FULL] = ARRAY_SIZE(is0_full_actionfield),
-	[VCAP_AFS_CLASS_REDUCED] = ARRAY_SIZE(is0_class_reduced_actionfield),
-};
-
-static int is2_actionfield_set_map_size[] = {
-	[VCAP_AFS_BASE_TYPE] = ARRAY_SIZE(is2_base_type_actionfield),
-};
-
-static int es0_actionfield_set_map_size[] = {
-	[VCAP_AFS_ES0] = ARRAY_SIZE(es0_es0_actionfield),
-};
-
-static int es2_actionfield_set_map_size[] = {
-	[VCAP_AFS_BASE_TYPE] = ARRAY_SIZE(es2_base_type_actionfield),
-};
-
-/* Type Groups */
-static const struct vcap_typegroup is0_x12_keyfield_set_typegroups[] = {
-	{
-		.offset = 0,
-		.width = 5,
-		.value = 16,
-	},
-	{
-		.offset = 52,
-		.width = 1,
-		.value = 0,
-	},
-	{
-		.offset = 104,
-		.width = 2,
-		.value = 0,
-	},
-	{
-		.offset = 156,
-		.width = 3,
-		.value = 0,
-	},
-	{
-		.offset = 208,
-		.width = 2,
-		.value = 0,
-	},
-	{
-		.offset = 260,
-		.width = 1,
-		.value = 0,
-	},
-	{
-		.offset = 312,
-		.width = 4,
-		.value = 0,
-	},
-	{
-		.offset = 364,
-		.width = 1,
-		.value = 0,
-	},
-	{
-		.offset = 416,
-		.width = 2,
-		.value = 0,
-	},
-	{
-		.offset = 468,
-		.width = 3,
-		.value = 0,
-	},
-	{
-		.offset = 520,
-		.width = 2,
-		.value = 0,
-	},
-	{
-		.offset = 572,
-		.width = 1,
-		.value = 0,
-	},
-	{}
-};
-
-static const struct vcap_typegroup is0_x6_keyfield_set_typegroups[] = {
-	{
-		.offset = 0,
-		.width = 4,
-		.value = 8,
-	},
-	{
-		.offset = 52,
-		.width = 1,
-		.value = 0,
-	},
-	{
-		.offset = 104,
-		.width = 2,
-		.value = 0,
-	},
-	{
-		.offset = 156,
-		.width = 3,
-		.value = 0,
-	},
-	{
-		.offset = 208,
-		.width = 2,
-		.value = 0,
-	},
-	{
-		.offset = 260,
-		.width = 1,
-		.value = 0,
-	},
-	{}
-};
-
-static const struct vcap_typegroup is0_x3_keyfield_set_typegroups[] = {
-	{}
-};
-
-static const struct vcap_typegroup is0_x2_keyfield_set_typegroups[] = {
-	{}
-};
-
-static const struct vcap_typegroup is0_x1_keyfield_set_typegroups[] = {
-	{}
-};
-
-static const struct vcap_typegroup is2_x12_keyfield_set_typegroups[] = {
-	{
-		.offset = 0,
-		.width = 3,
-		.value = 4,
-	},
-	{
-		.offset = 156,
-		.width = 1,
-		.value = 0,
-	},
-	{
-		.offset = 312,
-		.width = 2,
-		.value = 0,
-	},
-	{
-		.offset = 468,
-		.width = 1,
-		.value = 0,
-	},
-	{}
-};
-
-static const struct vcap_typegroup is2_x6_keyfield_set_typegroups[] = {
-	{
-		.offset = 0,
-		.width = 2,
-		.value = 2,
-	},
-	{
-		.offset = 156,
-		.width = 1,
-		.value = 0,
-	},
-	{}
-};
-
-static const struct vcap_typegroup is2_x3_keyfield_set_typegroups[] = {
-	{}
-};
-
-static const struct vcap_typegroup is2_x1_keyfield_set_typegroups[] = {
-	{}
-};
-
-static const struct vcap_typegroup es0_x1_keyfield_set_typegroups[] = {
-	{}
-};
-
-static const struct vcap_typegroup es2_x12_keyfield_set_typegroups[] = {
-	{
-		.offset = 0,
-		.width = 3,
-		.value = 4,
-	},
-	{
-		.offset = 156,
-		.width = 1,
-		.value = 0,
-	},
-	{
-		.offset = 312,
-		.width = 2,
-		.value = 0,
-	},
-	{
-		.offset = 468,
-		.width = 1,
-		.value = 0,
-	},
-	{}
-};
-
-static const struct vcap_typegroup es2_x6_keyfield_set_typegroups[] = {
-	{
-		.offset = 0,
-		.width = 2,
-		.value = 2,
-	},
-	{
-		.offset = 156,
-		.width = 1,
-		.value = 0,
-	},
-	{}
-};
-
-static const struct vcap_typegroup es2_x3_keyfield_set_typegroups[] = {
-	{}
-};
-
-static const struct vcap_typegroup es2_x1_keyfield_set_typegroups[] = {
-	{}
-};
-
-static const struct vcap_typegroup *is0_keyfield_set_typegroups[] = {
-	[12] = is0_x12_keyfield_set_typegroups,
-	[6] = is0_x6_keyfield_set_typegroups,
-	[3] = is0_x3_keyfield_set_typegroups,
-	[2] = is0_x2_keyfield_set_typegroups,
-	[1] = is0_x1_keyfield_set_typegroups,
-	[13] = NULL,
-};
-
-static const struct vcap_typegroup *is2_keyfield_set_typegroups[] = {
-	[12] = is2_x12_keyfield_set_typegroups,
-	[6] = is2_x6_keyfield_set_typegroups,
-	[3] = is2_x3_keyfield_set_typegroups,
-	[1] = is2_x1_keyfield_set_typegroups,
-	[13] = NULL,
-};
-
-static const struct vcap_typegroup *es0_keyfield_set_typegroups[] = {
-	[1] = es0_x1_keyfield_set_typegroups,
-	[2] = NULL,
-};
-
-static const struct vcap_typegroup *es2_keyfield_set_typegroups[] = {
-	[12] = es2_x12_keyfield_set_typegroups,
-	[6] = es2_x6_keyfield_set_typegroups,
-	[3] = es2_x3_keyfield_set_typegroups,
-	[1] = es2_x1_keyfield_set_typegroups,
-	[13] = NULL,
-};
-
-static const struct vcap_typegroup is0_x3_actionfield_set_typegroups[] = {
-	{
-		.offset = 0,
-		.width = 3,
-		.value = 4,
-	},
-	{
-		.offset = 103,
-		.width = 2,
-		.value = 0,
-	},
-	{
-		.offset = 206,
-		.width = 2,
-		.value = 0,
-	},
-	{}
-};
-
-static const struct vcap_typegroup is0_x2_actionfield_set_typegroups[] = {
-	{
-		.offset = 0,
-		.width = 2,
-		.value = 2,
-	},
-	{
-		.offset = 103,
-		.width = 1,
-		.value = 0,
-	},
-	{}
-};
-
-static const struct vcap_typegroup is0_x1_actionfield_set_typegroups[] = {
-	{
-		.offset = 0,
-		.width = 1,
-		.value = 1,
-	},
-	{}
-};
-
-static const struct vcap_typegroup is2_x3_actionfield_set_typegroups[] = {
-	{
-		.offset = 0,
-		.width = 2,
-		.value = 2,
-	},
-	{
-		.offset = 95,
-		.width = 1,
-		.value = 0,
-	},
-	{
-		.offset = 190,
-		.width = 1,
-		.value = 0,
-	},
-	{}
-};
-
-static const struct vcap_typegroup is2_x1_actionfield_set_typegroups[] = {
-	{}
-};
-
-static const struct vcap_typegroup es0_x1_actionfield_set_typegroups[] = {
-	{}
-};
-
-static const struct vcap_typegroup es2_x3_actionfield_set_typegroups[] = {
-	{
-		.offset = 0,
-		.width = 2,
-		.value = 2,
-	},
-	{
-		.offset = 19,
-		.width = 1,
-		.value = 0,
-	},
-	{
-		.offset = 38,
-		.width = 1,
-		.value = 0,
-	},
-	{}
-};
-
-static const struct vcap_typegroup es2_x1_actionfield_set_typegroups[] = {
-	{}
-};
-
-static const struct vcap_typegroup *is0_actionfield_set_typegroups[] = {
-	[3] = is0_x3_actionfield_set_typegroups,
-	[2] = is0_x2_actionfield_set_typegroups,
-	[1] = is0_x1_actionfield_set_typegroups,
-	[13] = NULL,
-};
-
-static const struct vcap_typegroup *is2_actionfield_set_typegroups[] = {
-	[3] = is2_x3_actionfield_set_typegroups,
-	[1] = is2_x1_actionfield_set_typegroups,
-	[13] = NULL,
-};
-
-static const struct vcap_typegroup *es0_actionfield_set_typegroups[] = {
-	[1] = es0_x1_actionfield_set_typegroups,
-	[2] = NULL,
-};
-
-static const struct vcap_typegroup *es2_actionfield_set_typegroups[] = {
-	[3] = es2_x3_actionfield_set_typegroups,
-	[1] = es2_x1_actionfield_set_typegroups,
-	[13] = NULL,
-};
-
-/* Keyfieldset names */
-static const char * const vcap_keyfield_set_names[] = {
-	[VCAP_KFS_NO_VALUE]                      =  "(None)",
-	[VCAP_KFS_ARP]                           =  "VCAP_KFS_ARP",
-	[VCAP_KFS_ETAG]                          =  "VCAP_KFS_ETAG",
-	[VCAP_KFS_IP4_OTHER]                     =  "VCAP_KFS_IP4_OTHER",
-	[VCAP_KFS_IP4_TCP_UDP]                   =  "VCAP_KFS_IP4_TCP_UDP",
-	[VCAP_KFS_IP4_VID]                       =  "VCAP_KFS_IP4_VID",
-	[VCAP_KFS_IP6_OTHER]                     =  "VCAP_KFS_IP6_OTHER",
-	[VCAP_KFS_IP6_STD]                       =  "VCAP_KFS_IP6_STD",
-	[VCAP_KFS_IP6_TCP_UDP]                   =  "VCAP_KFS_IP6_TCP_UDP",
-	[VCAP_KFS_IP6_VID]                       =  "VCAP_KFS_IP6_VID",
-	[VCAP_KFS_IP_7TUPLE]                     =  "VCAP_KFS_IP_7TUPLE",
-	[VCAP_KFS_ISDX]                          =  "VCAP_KFS_ISDX",
-	[VCAP_KFS_LL_FULL]                       =  "VCAP_KFS_LL_FULL",
-	[VCAP_KFS_MAC_ETYPE]                     =  "VCAP_KFS_MAC_ETYPE",
-	[VCAP_KFS_MAC_LLC]                       =  "VCAP_KFS_MAC_LLC",
-	[VCAP_KFS_MAC_SNAP]                      =  "VCAP_KFS_MAC_SNAP",
-	[VCAP_KFS_NORMAL_5TUPLE_IP4]             =  "VCAP_KFS_NORMAL_5TUPLE_IP4",
-	[VCAP_KFS_NORMAL_7TUPLE]                 =  "VCAP_KFS_NORMAL_7TUPLE",
-	[VCAP_KFS_OAM]                           =  "VCAP_KFS_OAM",
-	[VCAP_KFS_PURE_5TUPLE_IP4]               =  "VCAP_KFS_PURE_5TUPLE_IP4",
-	[VCAP_KFS_SMAC_SIP4]                     =  "VCAP_KFS_SMAC_SIP4",
-	[VCAP_KFS_SMAC_SIP6]                     =  "VCAP_KFS_SMAC_SIP6",
-};
-
-/* Actionfieldset names */
-static const char * const vcap_actionfield_set_names[] = {
-	[VCAP_AFS_NO_VALUE]                      =  "(None)",
-	[VCAP_AFS_BASE_TYPE]                     =  "VCAP_AFS_BASE_TYPE",
-	[VCAP_AFS_CLASSIFICATION]                =  "VCAP_AFS_CLASSIFICATION",
-	[VCAP_AFS_CLASS_REDUCED]                 =  "VCAP_AFS_CLASS_REDUCED",
-	[VCAP_AFS_ES0]                           =  "VCAP_AFS_ES0",
-	[VCAP_AFS_FULL]                          =  "VCAP_AFS_FULL",
-	[VCAP_AFS_SMAC_SIP]                      =  "VCAP_AFS_SMAC_SIP",
-};
-
-/* Keyfield names */
-static const char * const vcap_keyfield_names[] = {
-	[VCAP_KF_NO_VALUE]                       =  "(None)",
-	[VCAP_KF_8021BR_ECID_BASE]               =  "8021BR_ECID_BASE",
-	[VCAP_KF_8021BR_ECID_EXT]                =  "8021BR_ECID_EXT",
-	[VCAP_KF_8021BR_E_TAGGED]                =  "8021BR_E_TAGGED",
-	[VCAP_KF_8021BR_GRP]                     =  "8021BR_GRP",
-	[VCAP_KF_8021BR_IGR_ECID_BASE]           =  "8021BR_IGR_ECID_BASE",
-	[VCAP_KF_8021BR_IGR_ECID_EXT]            =  "8021BR_IGR_ECID_EXT",
-	[VCAP_KF_8021Q_DEI0]                     =  "8021Q_DEI0",
-	[VCAP_KF_8021Q_DEI1]                     =  "8021Q_DEI1",
-	[VCAP_KF_8021Q_DEI2]                     =  "8021Q_DEI2",
-	[VCAP_KF_8021Q_DEI_CLS]                  =  "8021Q_DEI_CLS",
-	[VCAP_KF_8021Q_PCP0]                     =  "8021Q_PCP0",
-	[VCAP_KF_8021Q_PCP1]                     =  "8021Q_PCP1",
-	[VCAP_KF_8021Q_PCP2]                     =  "8021Q_PCP2",
-	[VCAP_KF_8021Q_PCP_CLS]                  =  "8021Q_PCP_CLS",
-	[VCAP_KF_8021Q_TPID]                     =  "8021Q_TPID",
-	[VCAP_KF_8021Q_TPID0]                    =  "8021Q_TPID0",
-	[VCAP_KF_8021Q_TPID1]                    =  "8021Q_TPID1",
-	[VCAP_KF_8021Q_TPID2]                    =  "8021Q_TPID2",
-	[VCAP_KF_8021Q_VID0]                     =  "8021Q_VID0",
-	[VCAP_KF_8021Q_VID1]                     =  "8021Q_VID1",
-	[VCAP_KF_8021Q_VID2]                     =  "8021Q_VID2",
-	[VCAP_KF_8021Q_VID_CLS]                  =  "8021Q_VID_CLS",
-	[VCAP_KF_8021Q_VLAN_TAGGED_IS]           =  "8021Q_VLAN_TAGGED_IS",
-	[VCAP_KF_8021Q_VLAN_TAGS]                =  "8021Q_VLAN_TAGS",
-	[VCAP_KF_ACL_GRP_ID]                     =  "ACL_GRP_ID",
-	[VCAP_KF_ARP_ADDR_SPACE_OK_IS]           =  "ARP_ADDR_SPACE_OK_IS",
-	[VCAP_KF_ARP_LEN_OK_IS]                  =  "ARP_LEN_OK_IS",
-	[VCAP_KF_ARP_OPCODE]                     =  "ARP_OPCODE",
-	[VCAP_KF_ARP_OPCODE_UNKNOWN_IS]          =  "ARP_OPCODE_UNKNOWN_IS",
-	[VCAP_KF_ARP_PROTO_SPACE_OK_IS]          =  "ARP_PROTO_SPACE_OK_IS",
-	[VCAP_KF_ARP_SENDER_MATCH_IS]            =  "ARP_SENDER_MATCH_IS",
-	[VCAP_KF_ARP_TGT_MATCH_IS]               =  "ARP_TGT_MATCH_IS",
-	[VCAP_KF_COSID_CLS]                      =  "COSID_CLS",
-	[VCAP_KF_ES0_ISDX_KEY_ENA]               =  "ES0_ISDX_KEY_ENA",
-	[VCAP_KF_ETYPE]                          =  "ETYPE",
-	[VCAP_KF_ETYPE_LEN_IS]                   =  "ETYPE_LEN_IS",
-	[VCAP_KF_HOST_MATCH]                     =  "HOST_MATCH",
-	[VCAP_KF_IF_EGR_PORT_MASK]               =  "IF_EGR_PORT_MASK",
-	[VCAP_KF_IF_EGR_PORT_MASK_RNG]           =  "IF_EGR_PORT_MASK_RNG",
-	[VCAP_KF_IF_EGR_PORT_NO]                 =  "IF_EGR_PORT_NO",
-	[VCAP_KF_IF_IGR_PORT]                    =  "IF_IGR_PORT",
-	[VCAP_KF_IF_IGR_PORT_MASK]               =  "IF_IGR_PORT_MASK",
-	[VCAP_KF_IF_IGR_PORT_MASK_L3]            =  "IF_IGR_PORT_MASK_L3",
-	[VCAP_KF_IF_IGR_PORT_MASK_RNG]           =  "IF_IGR_PORT_MASK_RNG",
-	[VCAP_KF_IF_IGR_PORT_MASK_SEL]           =  "IF_IGR_PORT_MASK_SEL",
-	[VCAP_KF_IF_IGR_PORT_SEL]                =  "IF_IGR_PORT_SEL",
-	[VCAP_KF_IP4_IS]                         =  "IP4_IS",
-	[VCAP_KF_IP_MC_IS]                       =  "IP_MC_IS",
-	[VCAP_KF_IP_PAYLOAD_5TUPLE]              =  "IP_PAYLOAD_5TUPLE",
-	[VCAP_KF_IP_SNAP_IS]                     =  "IP_SNAP_IS",
-	[VCAP_KF_ISDX_CLS]                       =  "ISDX_CLS",
-	[VCAP_KF_ISDX_GT0_IS]                    =  "ISDX_GT0_IS",
-	[VCAP_KF_L2_BC_IS]                       =  "L2_BC_IS",
-	[VCAP_KF_L2_DMAC]                        =  "L2_DMAC",
-	[VCAP_KF_L2_FRM_TYPE]                    =  "L2_FRM_TYPE",
-	[VCAP_KF_L2_FWD_IS]                      =  "L2_FWD_IS",
-	[VCAP_KF_L2_LLC]                         =  "L2_LLC",
-	[VCAP_KF_L2_MC_IS]                       =  "L2_MC_IS",
-	[VCAP_KF_L2_PAYLOAD0]                    =  "L2_PAYLOAD0",
-	[VCAP_KF_L2_PAYLOAD1]                    =  "L2_PAYLOAD1",
-	[VCAP_KF_L2_PAYLOAD2]                    =  "L2_PAYLOAD2",
-	[VCAP_KF_L2_PAYLOAD_ETYPE]               =  "L2_PAYLOAD_ETYPE",
-	[VCAP_KF_L2_SMAC]                        =  "L2_SMAC",
-	[VCAP_KF_L2_SNAP]                        =  "L2_SNAP",
-	[VCAP_KF_L3_DIP_EQ_SIP_IS]               =  "L3_DIP_EQ_SIP_IS",
-	[VCAP_KF_L3_DPL_CLS]                     =  "L3_DPL_CLS",
-	[VCAP_KF_L3_DSCP]                        =  "L3_DSCP",
-	[VCAP_KF_L3_DST_IS]                      =  "L3_DST_IS",
-	[VCAP_KF_L3_FRAGMENT]                    =  "L3_FRAGMENT",
-	[VCAP_KF_L3_FRAGMENT_TYPE]               =  "L3_FRAGMENT_TYPE",
-	[VCAP_KF_L3_FRAG_INVLD_L4_LEN]           =  "L3_FRAG_INVLD_L4_LEN",
-	[VCAP_KF_L3_FRAG_OFS_GT0]                =  "L3_FRAG_OFS_GT0",
-	[VCAP_KF_L3_IP4_DIP]                     =  "L3_IP4_DIP",
-	[VCAP_KF_L3_IP4_SIP]                     =  "L3_IP4_SIP",
-	[VCAP_KF_L3_IP6_DIP]                     =  "L3_IP6_DIP",
-	[VCAP_KF_L3_IP6_SIP]                     =  "L3_IP6_SIP",
-	[VCAP_KF_L3_IP_PROTO]                    =  "L3_IP_PROTO",
-	[VCAP_KF_L3_OPTIONS_IS]                  =  "L3_OPTIONS_IS",
-	[VCAP_KF_L3_PAYLOAD]                     =  "L3_PAYLOAD",
-	[VCAP_KF_L3_RT_IS]                       =  "L3_RT_IS",
-	[VCAP_KF_L3_TOS]                         =  "L3_TOS",
-	[VCAP_KF_L3_TTL_GT0]                     =  "L3_TTL_GT0",
-	[VCAP_KF_L4_1588_DOM]                    =  "L4_1588_DOM",
-	[VCAP_KF_L4_1588_VER]                    =  "L4_1588_VER",
-	[VCAP_KF_L4_ACK]                         =  "L4_ACK",
-	[VCAP_KF_L4_DPORT]                       =  "L4_DPORT",
-	[VCAP_KF_L4_FIN]                         =  "L4_FIN",
-	[VCAP_KF_L4_PAYLOAD]                     =  "L4_PAYLOAD",
-	[VCAP_KF_L4_PSH]                         =  "L4_PSH",
-	[VCAP_KF_L4_RNG]                         =  "L4_RNG",
-	[VCAP_KF_L4_RST]                         =  "L4_RST",
-	[VCAP_KF_L4_SEQUENCE_EQ0_IS]             =  "L4_SEQUENCE_EQ0_IS",
-	[VCAP_KF_L4_SPORT]                       =  "L4_SPORT",
-	[VCAP_KF_L4_SPORT_EQ_DPORT_IS]           =  "L4_SPORT_EQ_DPORT_IS",
-	[VCAP_KF_L4_SYN]                         =  "L4_SYN",
-	[VCAP_KF_L4_URG]                         =  "L4_URG",
-	[VCAP_KF_LOOKUP_FIRST_IS]                =  "LOOKUP_FIRST_IS",
-	[VCAP_KF_LOOKUP_GEN_IDX]                 =  "LOOKUP_GEN_IDX",
-	[VCAP_KF_LOOKUP_GEN_IDX_SEL]             =  "LOOKUP_GEN_IDX_SEL",
-	[VCAP_KF_LOOKUP_PAG]                     =  "LOOKUP_PAG",
-	[VCAP_KF_MIRROR_PROBE]                   =  "MIRROR_PROBE",
-	[VCAP_KF_OAM_CCM_CNTS_EQ0]               =  "OAM_CCM_CNTS_EQ0",
-	[VCAP_KF_OAM_DETECTED]                   =  "OAM_DETECTED",
-	[VCAP_KF_OAM_FLAGS]                      =  "OAM_FLAGS",
-	[VCAP_KF_OAM_MEL_FLAGS]                  =  "OAM_MEL_FLAGS",
-	[VCAP_KF_OAM_MEPID]                      =  "OAM_MEPID",
-	[VCAP_KF_OAM_OPCODE]                     =  "OAM_OPCODE",
-	[VCAP_KF_OAM_VER]                        =  "OAM_VER",
-	[VCAP_KF_OAM_Y1731_IS]                   =  "OAM_Y1731_IS",
-	[VCAP_KF_PROT_ACTIVE]                    =  "PROT_ACTIVE",
-	[VCAP_KF_TCP_IS]                         =  "TCP_IS",
-	[VCAP_KF_TCP_UDP_IS]                     =  "TCP_UDP_IS",
-	[VCAP_KF_TYPE]                           =  "TYPE",
-};
-
-/* Actionfield names */
-static const char * const vcap_actionfield_names[] = {
-	[VCAP_AF_NO_VALUE]                       =  "(None)",
-	[VCAP_AF_ACL_ID]                         =  "ACL_ID",
-	[VCAP_AF_CLS_VID_SEL]                    =  "CLS_VID_SEL",
-	[VCAP_AF_CNT_ID]                         =  "CNT_ID",
-	[VCAP_AF_COPY_PORT_NUM]                  =  "COPY_PORT_NUM",
-	[VCAP_AF_COPY_QUEUE_NUM]                 =  "COPY_QUEUE_NUM",
-	[VCAP_AF_CPU_COPY_ENA]                   =  "CPU_COPY_ENA",
-	[VCAP_AF_CPU_QU]                         =  "CPU_QU",
-	[VCAP_AF_CPU_QUEUE_NUM]                  =  "CPU_QUEUE_NUM",
-	[VCAP_AF_DEI_A_VAL]                      =  "DEI_A_VAL",
-	[VCAP_AF_DEI_B_VAL]                      =  "DEI_B_VAL",
-	[VCAP_AF_DEI_C_VAL]                      =  "DEI_C_VAL",
-	[VCAP_AF_DEI_ENA]                        =  "DEI_ENA",
-	[VCAP_AF_DEI_VAL]                        =  "DEI_VAL",
-	[VCAP_AF_DP_ENA]                         =  "DP_ENA",
-	[VCAP_AF_DP_VAL]                         =  "DP_VAL",
-	[VCAP_AF_DSCP_ENA]                       =  "DSCP_ENA",
-	[VCAP_AF_DSCP_SEL]                       =  "DSCP_SEL",
-	[VCAP_AF_DSCP_VAL]                       =  "DSCP_VAL",
-	[VCAP_AF_ES2_REW_CMD]                    =  "ES2_REW_CMD",
-	[VCAP_AF_ESDX]                           =  "ESDX",
-	[VCAP_AF_FWD_KILL_ENA]                   =  "FWD_KILL_ENA",
-	[VCAP_AF_FWD_MODE]                       =  "FWD_MODE",
-	[VCAP_AF_FWD_SEL]                        =  "FWD_SEL",
-	[VCAP_AF_HIT_ME_ONCE]                    =  "HIT_ME_ONCE",
-	[VCAP_AF_HOST_MATCH]                     =  "HOST_MATCH",
-	[VCAP_AF_IGNORE_PIPELINE_CTRL]           =  "IGNORE_PIPELINE_CTRL",
-	[VCAP_AF_INTR_ENA]                       =  "INTR_ENA",
-	[VCAP_AF_ISDX_ADD_REPLACE_SEL]           =  "ISDX_ADD_REPLACE_SEL",
-	[VCAP_AF_ISDX_ENA]                       =  "ISDX_ENA",
-	[VCAP_AF_ISDX_VAL]                       =  "ISDX_VAL",
-	[VCAP_AF_LOOP_ENA]                       =  "LOOP_ENA",
-	[VCAP_AF_LRN_DIS]                        =  "LRN_DIS",
-	[VCAP_AF_MAP_IDX]                        =  "MAP_IDX",
-	[VCAP_AF_MAP_KEY]                        =  "MAP_KEY",
-	[VCAP_AF_MAP_LOOKUP_SEL]                 =  "MAP_LOOKUP_SEL",
-	[VCAP_AF_MASK_MODE]                      =  "MASK_MODE",
-	[VCAP_AF_MATCH_ID]                       =  "MATCH_ID",
-	[VCAP_AF_MATCH_ID_MASK]                  =  "MATCH_ID_MASK",
-	[VCAP_AF_MIRROR_ENA]                     =  "MIRROR_ENA",
-	[VCAP_AF_MIRROR_PROBE]                   =  "MIRROR_PROBE",
-	[VCAP_AF_MIRROR_PROBE_ID]                =  "MIRROR_PROBE_ID",
-	[VCAP_AF_NXT_IDX]                        =  "NXT_IDX",
-	[VCAP_AF_NXT_IDX_CTRL]                   =  "NXT_IDX_CTRL",
-	[VCAP_AF_PAG_OVERRIDE_MASK]              =  "PAG_OVERRIDE_MASK",
-	[VCAP_AF_PAG_VAL]                        =  "PAG_VAL",
-	[VCAP_AF_PCP_A_VAL]                      =  "PCP_A_VAL",
-	[VCAP_AF_PCP_B_VAL]                      =  "PCP_B_VAL",
-	[VCAP_AF_PCP_C_VAL]                      =  "PCP_C_VAL",
-	[VCAP_AF_PCP_ENA]                        =  "PCP_ENA",
-	[VCAP_AF_PCP_VAL]                        =  "PCP_VAL",
-	[VCAP_AF_PIPELINE_ACT]                   =  "PIPELINE_ACT",
-	[VCAP_AF_PIPELINE_FORCE_ENA]             =  "PIPELINE_FORCE_ENA",
-	[VCAP_AF_PIPELINE_PT]                    =  "PIPELINE_PT",
-	[VCAP_AF_POLICE_ENA]                     =  "POLICE_ENA",
-	[VCAP_AF_POLICE_IDX]                     =  "POLICE_IDX",
-	[VCAP_AF_POLICE_REMARK]                  =  "POLICE_REMARK",
-	[VCAP_AF_POLICE_VCAP_ONLY]               =  "POLICE_VCAP_ONLY",
-	[VCAP_AF_POP_VAL]                        =  "POP_VAL",
-	[VCAP_AF_PORT_MASK]                      =  "PORT_MASK",
-	[VCAP_AF_PUSH_CUSTOMER_TAG]              =  "PUSH_CUSTOMER_TAG",
-	[VCAP_AF_PUSH_INNER_TAG]                 =  "PUSH_INNER_TAG",
-	[VCAP_AF_PUSH_OUTER_TAG]                 =  "PUSH_OUTER_TAG",
-	[VCAP_AF_QOS_ENA]                        =  "QOS_ENA",
-	[VCAP_AF_QOS_VAL]                        =  "QOS_VAL",
-	[VCAP_AF_REW_OP]                         =  "REW_OP",
-	[VCAP_AF_RT_DIS]                         =  "RT_DIS",
-	[VCAP_AF_SWAP_MACS_ENA]                  =  "SWAP_MACS_ENA",
-	[VCAP_AF_TAG_A_DEI_SEL]                  =  "TAG_A_DEI_SEL",
-	[VCAP_AF_TAG_A_PCP_SEL]                  =  "TAG_A_PCP_SEL",
-	[VCAP_AF_TAG_A_TPID_SEL]                 =  "TAG_A_TPID_SEL",
-	[VCAP_AF_TAG_A_VID_SEL]                  =  "TAG_A_VID_SEL",
-	[VCAP_AF_TAG_B_DEI_SEL]                  =  "TAG_B_DEI_SEL",
-	[VCAP_AF_TAG_B_PCP_SEL]                  =  "TAG_B_PCP_SEL",
-	[VCAP_AF_TAG_B_TPID_SEL]                 =  "TAG_B_TPID_SEL",
-	[VCAP_AF_TAG_B_VID_SEL]                  =  "TAG_B_VID_SEL",
-	[VCAP_AF_TAG_C_DEI_SEL]                  =  "TAG_C_DEI_SEL",
-	[VCAP_AF_TAG_C_PCP_SEL]                  =  "TAG_C_PCP_SEL",
-	[VCAP_AF_TAG_C_TPID_SEL]                 =  "TAG_C_TPID_SEL",
-	[VCAP_AF_TAG_C_VID_SEL]                  =  "TAG_C_VID_SEL",
-	[VCAP_AF_TYPE]                           =  "TYPE",
-	[VCAP_AF_UNTAG_VID_ENA]                  =  "UNTAG_VID_ENA",
-	[VCAP_AF_VID_A_VAL]                      =  "VID_A_VAL",
-	[VCAP_AF_VID_B_VAL]                      =  "VID_B_VAL",
-	[VCAP_AF_VID_C_VAL]                      =  "VID_C_VAL",
-	[VCAP_AF_VID_VAL]                        =  "VID_VAL",
-};
-
-/* VCAPs */
-const struct vcap_info lan969x_vcaps[] = {
-	[VCAP_TYPE_IS0] = {
-		.name = "is0",
-		.rows = 256,
-		.sw_count = 12,
-		.sw_width = 52,
-		.sticky_width = 1,
-		.act_width = 103,
-		.default_cnt = 70,
-		.require_cnt_dis = 0,
-		.version = 1,
-		.keyfield_set = is0_keyfield_set,
-		.keyfield_set_size = ARRAY_SIZE(is0_keyfield_set),
-		.actionfield_set = is0_actionfield_set,
-		.actionfield_set_size = ARRAY_SIZE(is0_actionfield_set),
-		.keyfield_set_map = is0_keyfield_set_map,
-		.keyfield_set_map_size = is0_keyfield_set_map_size,
-		.actionfield_set_map = is0_actionfield_set_map,
-		.actionfield_set_map_size = is0_actionfield_set_map_size,
-		.keyfield_set_typegroups = is0_keyfield_set_typegroups,
-		.actionfield_set_typegroups = is0_actionfield_set_typegroups,
-	},
-	[VCAP_TYPE_IS2] = {
-		.name = "is2",
-		.rows = 256,
-		.sw_count = 12,
-		.sw_width = 52,
-		.sticky_width = 1,
-		.act_width = 103,
-		.default_cnt = 38,
-		.require_cnt_dis = 0,
-		.version = 1,
-		.keyfield_set = is2_keyfield_set,
-		.keyfield_set_size = ARRAY_SIZE(is2_keyfield_set),
-		.actionfield_set = is2_actionfield_set,
-		.actionfield_set_size = ARRAY_SIZE(is2_actionfield_set),
-		.keyfield_set_map = is2_keyfield_set_map,
-		.keyfield_set_map_size = is2_keyfield_set_map_size,
-		.actionfield_set_map = is2_actionfield_set_map,
-		.actionfield_set_map_size = is2_actionfield_set_map_size,
-		.keyfield_set_typegroups = is2_keyfield_set_typegroups,
-		.actionfield_set_typegroups = is2_actionfield_set_typegroups,
-	},
-	[VCAP_TYPE_ES0] = {
-		.name = "es0",
-		.rows = 1536,
-		.sw_count = 1,
-		.sw_width = 51,
-		.sticky_width = 1,
-		.act_width = 469,
-		.default_cnt = 35,
-		.require_cnt_dis = 0,
-		.version = 1,
-		.keyfield_set = es0_keyfield_set,
-		.keyfield_set_size = ARRAY_SIZE(es0_keyfield_set),
-		.actionfield_set = es0_actionfield_set,
-		.actionfield_set_size = ARRAY_SIZE(es0_actionfield_set),
-		.keyfield_set_map = es0_keyfield_set_map,
-		.keyfield_set_map_size = es0_keyfield_set_map_size,
-		.actionfield_set_map = es0_actionfield_set_map,
-		.actionfield_set_map_size = es0_actionfield_set_map_size,
-		.keyfield_set_typegroups = es0_keyfield_set_typegroups,
-		.actionfield_set_typegroups = es0_actionfield_set_typegroups,
-	},
-	[VCAP_TYPE_ES2] = {
-		.name = "es2",
-		.rows = 256,
-		.sw_count = 12,
-		.sw_width = 52,
-		.sticky_width = 1,
-		.act_width = 19,
-		.default_cnt = 39,
-		.require_cnt_dis = 0,
-		.version = 1,
-		.keyfield_set = es2_keyfield_set,
-		.keyfield_set_size = ARRAY_SIZE(es2_keyfield_set),
-		.actionfield_set = es2_actionfield_set,
-		.actionfield_set_size = ARRAY_SIZE(es2_actionfield_set),
-		.keyfield_set_map = es2_keyfield_set_map,
-		.keyfield_set_map_size = es2_keyfield_set_map_size,
-		.actionfield_set_map = es2_actionfield_set_map,
-		.actionfield_set_map_size = es2_actionfield_set_map_size,
-		.keyfield_set_typegroups = es2_keyfield_set_typegroups,
-		.actionfield_set_typegroups = es2_actionfield_set_typegroups,
-	},
-};
-
-const struct vcap_statistics lan969x_vcap_stats = {
-	.name = "lan969x",
-	.count = 4,
-	.keyfield_set_names = vcap_keyfield_set_names,
-	.actionfield_set_names = vcap_actionfield_set_names,
-	.keyfield_names = vcap_keyfield_names,
-	.actionfield_names = vcap_actionfield_names,
-};
--- a/drivers/net/ethernet/microchip/lan969x/lan969x_vcap_impl.c
+++ /dev/null
@@ -1,85 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-
-#include "vcap_api.h"
-#include "lan969x.h"
-
-const struct sparx5_vcap_inst lan969x_vcap_inst_cfg[] = {
-	{
-		.vtype = VCAP_TYPE_IS0, /* CLM-0 */
-		.vinst = 0,
-		.map_id = 1,
-		.lookups = SPARX5_IS0_LOOKUPS,
-		.lookups_per_instance = SPARX5_IS0_LOOKUPS / 3,
-		.first_cid = SPARX5_VCAP_CID_IS0_L0,
-		.last_cid = SPARX5_VCAP_CID_IS0_L2 - 1,
-		.blockno = 2,
-		.blocks = 1,
-		.ingress = true,
-	},
-	{
-		.vtype = VCAP_TYPE_IS0, /* CLM-1 */
-		.vinst = 1,
-		.map_id = 2,
-		.lookups = SPARX5_IS0_LOOKUPS,
-		.lookups_per_instance = SPARX5_IS0_LOOKUPS / 3,
-		.first_cid = SPARX5_VCAP_CID_IS0_L2,
-		.last_cid = SPARX5_VCAP_CID_IS0_L4 - 1,
-		.blockno = 3,
-		.blocks = 1,
-		.ingress = true,
-	},
-	{
-		.vtype = VCAP_TYPE_IS0, /* CLM-2 */
-		.vinst = 2,
-		.map_id = 3,
-		.lookups = SPARX5_IS0_LOOKUPS,
-		.lookups_per_instance = SPARX5_IS0_LOOKUPS / 3,
-		.first_cid = SPARX5_VCAP_CID_IS0_L4,
-		.last_cid = SPARX5_VCAP_CID_IS0_MAX,
-		.blockno = 4,
-		.blocks = 1,
-		.ingress = true,
-	},
-	{
-		.vtype = VCAP_TYPE_IS2, /* IS2-0 */
-		.vinst = 0,
-		.map_id = 4,
-		.lookups = SPARX5_IS2_LOOKUPS,
-		.lookups_per_instance = SPARX5_IS2_LOOKUPS / 2,
-		.first_cid = SPARX5_VCAP_CID_IS2_L0,
-		.last_cid = SPARX5_VCAP_CID_IS2_L2 - 1,
-		.blockno = 0,
-		.blocks = 1,
-		.ingress = true,
-	},
-	{
-		.vtype = VCAP_TYPE_IS2, /* IS2-1 */
-		.vinst = 1,
-		.map_id = 5,
-		.lookups = SPARX5_IS2_LOOKUPS,
-		.lookups_per_instance = SPARX5_IS2_LOOKUPS / 2,
-		.first_cid = SPARX5_VCAP_CID_IS2_L2,
-		.last_cid = SPARX5_VCAP_CID_IS2_MAX,
-		.blockno = 1,
-		.blocks = 1,
-		.ingress = true,
-	},
-	{
-		.vtype = VCAP_TYPE_ES0,
-		.lookups = SPARX5_ES0_LOOKUPS,
-		.lookups_per_instance = SPARX5_ES0_LOOKUPS,
-		.first_cid = SPARX5_VCAP_CID_ES0_L0,
-		.last_cid = SPARX5_VCAP_CID_ES0_MAX,
-		.count = 1536,
-		.ingress = false,
-	},
-	{
-		.vtype = VCAP_TYPE_ES2,
-		.lookups = SPARX5_ES2_LOOKUPS,
-		.lookups_per_instance = SPARX5_ES2_LOOKUPS,
-		.first_cid = SPARX5_VCAP_CID_ES2_L0,
-		.last_cid = SPARX5_VCAP_CID_ES2_MAX,
-		.count = 1024,
-		.ingress = false,
-	},
-};
--- /dev/null
+++ b/drivers/net/ethernet/microchip/sparx5/lan969x/lan969x.h
@@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/* Microchip lan969x Switch driver
+ *
+ * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries.
+ */
+
+#ifndef __LAN969X_H__
+#define __LAN969X_H__
+
+#include "../sparx5/sparx5_main.h"
+#include "../sparx5/sparx5_regs.h"
+#include "../sparx5/sparx5_vcap_impl.h"
+
+/* lan969x.c */
+extern const struct sparx5_match_data lan969x_desc;
+
+/* lan969x_vcap_ag_api.c */
+extern const struct vcap_statistics lan969x_vcap_stats;
+extern const struct vcap_info lan969x_vcaps[];
+
+/* lan969x_vcap_impl.c */
+extern const struct sparx5_vcap_inst lan969x_vcap_inst_cfg[];
+
+/* lan969x_regs.c */
+extern const unsigned int lan969x_tsize[TSIZE_LAST];
+extern const unsigned int lan969x_raddr[RADDR_LAST];
+extern const unsigned int lan969x_rcnt[RCNT_LAST];
+extern const unsigned int lan969x_gaddr[GADDR_LAST];
+extern const unsigned int lan969x_gcnt[GCNT_LAST];
+extern const unsigned int lan969x_gsize[GSIZE_LAST];
+extern const unsigned int lan969x_fpos[FPOS_LAST];
+extern const unsigned int lan969x_fsize[FSIZE_LAST];
+
+static inline bool lan969x_port_is_2g5(int portno)
+{
+	return portno == 1  || portno == 2  || portno == 3  ||
+	       portno == 5  || portno == 6  || portno == 7  ||
+	       portno == 10 || portno == 11 || portno == 14 ||
+	       portno == 15 || portno == 18 || portno == 19 ||
+	       portno == 22 || portno == 23;
+}
+
+static inline bool lan969x_port_is_5g(int portno)
+{
+	return portno == 9 || portno == 13 || portno == 17 ||
+	       portno == 21;
+}
+
+static inline bool lan969x_port_is_10g(int portno)
+{
+	return portno == 0  || portno == 4  || portno == 8  ||
+	       portno == 12 || portno == 16 || portno == 20 ||
+	       portno == 24 || portno == 25 || portno == 26 ||
+	       portno == 27;
+}
+
+static inline bool lan969x_port_is_25g(int portno)
+{
+	return false;
+}
+
+/* lan969x_calendar.c */
+int lan969x_dsm_calendar_calc(struct sparx5 *sparx5, u32 taxi,
+			      struct sparx5_calendar_data *data);
+#endif
--- /dev/null
+++ b/drivers/net/ethernet/microchip/sparx5/lan969x/lan969x_calendar.c
@@ -0,0 +1,191 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Microchip lan969x Switch driver
+ *
+ * Copyright (c) 2024 Microchip Technology Inc. and its subsidiaries.
+ */
+
+#include "lan969x.h"
+
+#define LAN969X_DSM_CAL_DEVS_PER_TAXI 10
+#define LAN969X_DSM_CAL_TAXIS 5
+
+enum lan969x_dsm_cal_dev {
+	DSM_CAL_DEV_2G5,
+	DSM_CAL_DEV_5G,
+	DSM_CAL_DEV_10G,
+	DSM_CAL_DEV_OTHER, /* 1G or less */
+	DSM_CAL_DEV_MAX
+};
+
+/* Each entry in the following struct defines properties for a given speed
+ * (10G, 5G, 2.5G, or 1G or less).
+ */
+struct lan969x_dsm_cal_dev_speed {
+	/* Number of devices that requires this speed. */
+	u32 n_devs;
+
+	/* Array of devices that requires this speed. */
+	u32 devs[LAN969X_DSM_CAL_DEVS_PER_TAXI];
+
+	/* Number of slots required for one device running this speed. */
+	u32 n_slots;
+
+	/* Gap between two slots for one device running this speed. */
+	u32 gap;
+};
+
+static u32
+lan969x_taxi_ports[LAN969X_DSM_CAL_TAXIS][LAN969X_DSM_CAL_DEVS_PER_TAXI] = {
+	{  0,  4,  1,  2,  3,  5,  6,  7, 28, 29 },
+	{  8, 12,  9, 13, 10, 11, 14, 15, 99, 99 },
+	{ 16, 20, 17, 21, 18, 19, 22, 23, 99, 99 },
+	{ 24, 25, 99, 99, 99, 99, 99, 99, 99, 99 },
+	{ 26, 27, 99, 99, 99, 99, 99, 99, 99, 99 }
+};
+
+static int lan969x_dsm_cal_idx_get(u32 *calendar, u32 cal_len, u32 *cal_idx)
+{
+	if (*cal_idx >= cal_len)
+		return -EINVAL;
+
+	do {
+		if (calendar[*cal_idx] == SPX5_DSM_CAL_EMPTY)
+			return 0;
+
+		(*cal_idx)++;
+	} while (*cal_idx < cal_len);
+
+	return -ENOENT;
+}
+
+static enum lan969x_dsm_cal_dev lan969x_dsm_cal_get_dev(int speed)
+{
+	return (speed == 10000 ? DSM_CAL_DEV_10G :
+		speed == 5000  ? DSM_CAL_DEV_5G :
+		speed == 2500  ? DSM_CAL_DEV_2G5 :
+				 DSM_CAL_DEV_OTHER);
+}
+
+static int lan969x_dsm_cal_get_speed(enum lan969x_dsm_cal_dev dev)
+{
+	return (dev == DSM_CAL_DEV_10G ? 10000 :
+		dev == DSM_CAL_DEV_5G  ? 5000 :
+		dev == DSM_CAL_DEV_2G5 ? 2500 :
+					 1000);
+}
+
+int lan969x_dsm_calendar_calc(struct sparx5 *sparx5, u32 taxi,
+			      struct sparx5_calendar_data *data)
+{
+	struct lan969x_dsm_cal_dev_speed dev_speeds[DSM_CAL_DEV_MAX] = {};
+	u32 cal_len, n_slots, taxi_bw, n_devs = 0, required_bw  = 0;
+	struct lan969x_dsm_cal_dev_speed *speed;
+	int err;
+
+	/* Maximum bandwidth for this taxi */
+	taxi_bw = (128 * 1000000) / sparx5_clk_period(sparx5->coreclock);
+
+	memcpy(data->taxi_ports, &lan969x_taxi_ports[taxi],
+	       LAN969X_DSM_CAL_DEVS_PER_TAXI * sizeof(u32));
+
+	for (int i = 0; i < LAN969X_DSM_CAL_DEVS_PER_TAXI; i++) {
+		u32 portno = data->taxi_ports[i];
+		enum sparx5_cal_bw bw;
+
+		bw = sparx5_get_port_cal_speed(sparx5, portno);
+
+		if (portno < sparx5->data->consts->n_ports_all)
+			data->taxi_speeds[i] = sparx5_cal_speed_to_value(bw);
+		else
+			data->taxi_speeds[i] = 0;
+	}
+
+	/* Determine the different port types (10G, 5G, 2.5G, <= 1G) in the
+	 * this taxi map.
+	 */
+	for (int i = 0; i < LAN969X_DSM_CAL_DEVS_PER_TAXI; i++) {
+		u32 taxi_speed = data->taxi_speeds[i];
+		enum lan969x_dsm_cal_dev dev;
+
+		if (taxi_speed == 0)
+			continue;
+
+		required_bw += taxi_speed;
+
+		dev = lan969x_dsm_cal_get_dev(taxi_speed);
+		speed = &dev_speeds[dev];
+		speed->devs[speed->n_devs++] = i;
+		n_devs++;
+	}
+
+	if (required_bw > taxi_bw) {
+		pr_err("Required bandwidth: %u is higher than total taxi bandwidth: %u",
+		       required_bw, taxi_bw);
+		return -EINVAL;
+	}
+
+	if (n_devs == 0) {
+		data->schedule[0] = SPX5_DSM_CAL_EMPTY;
+		return 0;
+	}
+
+	cal_len = n_devs;
+
+	/* Search for a calendar length that fits all active devices. */
+	while (cal_len < SPX5_DSM_CAL_LEN) {
+		u32 bw_per_slot = taxi_bw / cal_len;
+
+		n_slots = 0;
+
+		for (int i = 0; i < DSM_CAL_DEV_MAX; i++) {
+			speed = &dev_speeds[i];
+
+			if (speed->n_devs == 0)
+				continue;
+
+			required_bw = lan969x_dsm_cal_get_speed(i);
+			speed->n_slots = DIV_ROUND_UP(required_bw, bw_per_slot);
+
+			if (speed->n_slots)
+				speed->gap = DIV_ROUND_UP(cal_len,
+							  speed->n_slots);
+			else
+				speed->gap = 0;
+
+			n_slots += speed->n_slots * speed->n_devs;
+		}
+
+		if (n_slots <= cal_len)
+			break; /* Found a suitable calendar length. */
+
+		/* Not good enough yet. */
+		cal_len = n_slots;
+	}
+
+	if (cal_len > SPX5_DSM_CAL_LEN) {
+		pr_err("Invalid length: %u for taxi: %u", cal_len, taxi);
+		return -EINVAL;
+	}
+
+	for (u32 i = 0; i < SPX5_DSM_CAL_LEN; i++)
+		data->schedule[i] = SPX5_DSM_CAL_EMPTY;
+
+	/* Place the remaining devices */
+	for (u32 i = 0; i < DSM_CAL_DEV_MAX; i++) {
+		speed = &dev_speeds[i];
+		for (u32 dev = 0; dev < speed->n_devs; dev++) {
+			u32 idx = 0;
+
+			for (n_slots = 0; n_slots < speed->n_slots; n_slots++) {
+				err = lan969x_dsm_cal_idx_get(data->schedule,
+							      cal_len, &idx);
+				if (err)
+					return err;
+				data->schedule[idx] = speed->devs[dev];
+				idx += speed->gap;
+			}
+		}
+	}
+
+	return 0;
+}
--- /dev/null
+++ b/drivers/net/ethernet/microchip/sparx5/lan969x/lan969x_regs.c
@@ -0,0 +1,222 @@
+// SPDX-License-Identifier: GPL-2.0+
+/* Microchip lan969x Switch driver
+ *
+ * Copyright (c) 2024 Microchip Technology Inc.
+ */
+
+/* This file is autogenerated by cml-utils 2024-09-30 11:48:29 +0200.
+ * Commit ID: 9d07b8d19363f3cd3590ddb3f7a2e2768e16524b
+ */
+
+#include "lan969x.h"
+
+const unsigned int lan969x_tsize[TSIZE_LAST] = {
+	[TC_DEV10G] = 10,
+	[TC_DEV2G5] = 28,
+	[TC_DEV5G] = 4,
+	[TC_PCS10G_BR] = 10,
+	[TC_PCS5G_BR] = 4,
+};
+
+const unsigned int lan969x_raddr[RADDR_LAST] = {
+	[RA_CPU_PROC_CTRL] = 160,
+	[RA_GCB_SOFT_RST] = 12,
+	[RA_GCB_HW_SGPIO_TO_SD_MAP_CFG] = 20,
+};
+
+const unsigned int lan969x_rcnt[RCNT_LAST] = {
+	[RC_ANA_AC_OWN_UPSID] = 1,
+	[RC_ANA_ACL_VCAP_S2_CFG] = 35,
+	[RC_ANA_ACL_OWN_UPSID] = 1,
+	[RC_ANA_CL_OWN_UPSID] = 1,
+	[RC_ANA_L2_OWN_UPSID] = 1,
+	[RC_ASM_PORT_CFG] = 32,
+	[RC_DSM_BUF_CFG] = 32,
+	[RC_DSM_DEV_TX_STOP_WM_CFG] = 32,
+	[RC_DSM_RX_PAUSE_CFG] = 32,
+	[RC_DSM_MAC_CFG] = 32,
+	[RC_DSM_MAC_ADDR_BASE_HIGH_CFG] = 30,
+	[RC_DSM_MAC_ADDR_BASE_LOW_CFG] = 30,
+	[RC_DSM_TAXI_CAL_CFG] = 6,
+	[RC_GCB_HW_SGPIO_TO_SD_MAP_CFG] = 30,
+	[RC_HSCH_PORT_MODE] = 35,
+	[RC_QFWD_SWITCH_PORT_MODE] = 35,
+	[RC_QSYS_PAUSE_CFG] = 35,
+	[RC_QSYS_ATOP] = 35,
+	[RC_QSYS_FWD_PRESSURE] = 35,
+	[RC_QSYS_CAL_AUTO] = 4,
+	[RC_REW_OWN_UPSID] = 1,
+	[RC_REW_RTAG_ETAG_CTRL] = 35,
+};
+
+const unsigned int lan969x_gaddr[GADDR_LAST] = {
+	[GA_ANA_AC_RAM_CTRL] = 202000,
+	[GA_ANA_AC_PS_COMMON] = 202880,
+	[GA_ANA_AC_MIRROR_PROBE] = 203232,
+	[GA_ANA_AC_SRC] = 201728,
+	[GA_ANA_AC_PGID] = 131072,
+	[GA_ANA_AC_TSN_SF] = 202028,
+	[GA_ANA_AC_TSN_SF_CFG] = 148480,
+	[GA_ANA_AC_TSN_SF_STATUS] = 147936,
+	[GA_ANA_AC_SG_ACCESS] = 202032,
+	[GA_ANA_AC_SG_CONFIG] = 202752,
+	[GA_ANA_AC_SG_STATUS] = 147952,
+	[GA_ANA_AC_SG_STATUS_STICKY] = 202044,
+	[GA_ANA_AC_STAT_GLOBAL_CFG_PORT] = 202048,
+	[GA_ANA_AC_STAT_CNT_CFG_PORT] = 204800,
+	[GA_ANA_AC_STAT_GLOBAL_CFG_ACL] = 202068,
+	[GA_ANA_ACL_COMMON] = 8192,
+	[GA_ANA_ACL_KEY_SEL] = 9204,
+	[GA_ANA_ACL_CNT_B] = 4096,
+	[GA_ANA_ACL_STICKY] = 10852,
+	[GA_ANA_AC_POL_POL_ALL_CFG] = 17504,
+	[GA_ANA_AC_POL_COMMON_BDLB] = 19464,
+	[GA_ANA_AC_POL_COMMON_BUM_SLB] = 19472,
+	[GA_ANA_AC_SDLB_LBGRP_TBL] = 31788,
+	[GA_ANA_CL_PORT] = 65536,
+	[GA_ANA_CL_COMMON] = 87040,
+	[GA_ANA_L2_COMMON] = 561928,
+	[GA_ANA_L3_COMMON] = 370752,
+	[GA_ANA_L3_VLAN_ARP_L3MC_STICKY] = 368580,
+	[GA_ASM_CFG] = 18304,
+	[GA_ASM_PFC_TIMER_CFG] = 15568,
+	[GA_ASM_LBK_WM_CFG] = 15596,
+	[GA_ASM_LBK_MISC_CFG] = 15608,
+	[GA_ASM_RAM_CTRL] = 15684,
+	[GA_EACL_ES2_KEY_SELECT_PROFILE] = 36864,
+	[GA_EACL_CNT_TBL] = 30720,
+	[GA_EACL_POL_CFG] = 38400,
+	[GA_EACL_ES2_STICKY] = 29072,
+	[GA_EACL_RAM_CTRL] = 29112,
+	[GA_GCB_SIO_CTRL] = 560,
+	[GA_HSCH_HSCH_DWRR] = 36480,
+	[GA_HSCH_HSCH_MISC] = 36608,
+	[GA_HSCH_HSCH_LEAK_LISTS] = 37256,
+	[GA_HSCH_SYSTEM] = 37384,
+	[GA_HSCH_MMGT] = 36260,
+	[GA_HSCH_TAS_CONFIG] = 37696,
+	[GA_PTP_PTP_CFG] = 512,
+	[GA_PTP_PTP_TOD_DOMAINS] = 528,
+	[GA_PTP_PHASE_DETECTOR_CTRL] = 628,
+	[GA_QSYS_CALCFG] = 2164,
+	[GA_QSYS_RAM_CTRL] = 2204,
+	[GA_REW_COMMON] = 98304,
+	[GA_REW_PORT] = 49152,
+	[GA_REW_VOE_PORT_LM_CNT] = 90112,
+	[GA_REW_RAM_CTRL] = 93992,
+	[GA_VOP_RAM_CTRL] = 16368,
+	[GA_XQS_SYSTEM] = 5744,
+	[GA_XQS_QLIMIT_SHR] = 6912,
+};
+
+const unsigned int lan969x_gcnt[GCNT_LAST] = {
+	[GC_ANA_AC_SRC] = 67,
+	[GC_ANA_AC_PGID] = 1054,
+	[GC_ANA_AC_TSN_SF_CFG] = 256,
+	[GC_ANA_AC_STAT_CNT_CFG_PORT] = 35,
+	[GC_ANA_ACL_KEY_SEL] = 99,
+	[GC_ANA_ACL_CNT_A] = 1024,
+	[GC_ANA_ACL_CNT_B] = 1024,
+	[GC_ANA_AC_SDLB_LBGRP_TBL] = 5,
+	[GC_ANA_AC_SDLB_LBSET_TBL] = 496,
+	[GC_ANA_CL_PORT] = 35,
+	[GC_ANA_L2_ISDX_LIMIT] = 256,
+	[GC_ANA_L2_ISDX] = 1024,
+	[GC_ANA_L3_VLAN] = 4608,
+	[GC_ASM_DEV_STATISTICS] = 30,
+	[GC_EACL_ES2_KEY_SELECT_PROFILE] = 68,
+	[GC_EACL_CNT_TBL] = 512,
+	[GC_GCB_SIO_CTRL] = 1,
+	[GC_HSCH_HSCH_CFG] = 1120,
+	[GC_HSCH_HSCH_DWRR] = 32,
+	[GC_PTP_PTP_PINS] = 8,
+	[GC_PTP_PHASE_DETECTOR_CTRL] = 8,
+	[GC_REW_PORT] = 35,
+	[GC_REW_VOE_PORT_LM_CNT] = 240,
+};
+
+const unsigned int lan969x_gsize[GSIZE_LAST] = {
+	[GW_ANA_AC_SRC] = 4,
+	[GW_ANA_L2_COMMON] = 712,
+	[GW_ASM_CFG] = 1092,
+	[GW_CPU_CPU_REGS] = 180,
+	[GW_DEV2G5_PHASE_DETECTOR_CTRL] = 12,
+	[GW_FDMA_FDMA] = 448,
+	[GW_GCB_CHIP_REGS] = 180,
+	[GW_HSCH_TAS_CONFIG] = 16,
+	[GW_PTP_PHASE_DETECTOR_CTRL] = 12,
+	[GW_QSYS_PAUSE_CFG] = 988,
+};
+
+const unsigned int lan969x_fpos[FPOS_LAST] = {
+	[FP_CPU_PROC_CTRL_AARCH64_MODE_ENA] = 7,
+	[FP_CPU_PROC_CTRL_L2_RST_INVALIDATE_DIS] = 6,
+	[FP_CPU_PROC_CTRL_L1_RST_INVALIDATE_DIS] = 5,
+	[FP_CPU_PROC_CTRL_BE_EXCEP_MODE] = 4,
+	[FP_CPU_PROC_CTRL_VINITHI] = 3,
+	[FP_CPU_PROC_CTRL_CFGTE] = 2,
+	[FP_CPU_PROC_CTRL_CP15S_DISABLE] = 1,
+	[FP_CPU_PROC_CTRL_PROC_CRYPTO_DISABLE] = 0,
+	[FP_CPU_PROC_CTRL_L2_FLUSH_REQ] = 8,
+	[FP_DEV2G5_PHAD_CTRL_PHAD_ENA] = 5,
+	[FP_DEV2G5_PHAD_CTRL_PHAD_FAILED] = 3,
+	[FP_FDMA_CH_CFG_CH_XTR_STATUS_MODE] = 5,
+	[FP_FDMA_CH_CFG_CH_INTR_DB_EOF_ONLY] = 4,
+	[FP_FDMA_CH_CFG_CH_INJ_PORT] = 3,
+	[FP_PTP_PTP_PIN_CFG_PTP_PIN_ACTION] = 27,
+	[FP_PTP_PTP_PIN_CFG_PTP_PIN_SYNC] = 25,
+	[FP_PTP_PTP_PIN_CFG_PTP_PIN_INV_POL] = 24,
+	[FP_PTP_PHAD_CTRL_PHAD_ENA] = 5,
+	[FP_PTP_PHAD_CTRL_PHAD_FAILED] = 3,
+};
+
+const unsigned int lan969x_fsize[FSIZE_LAST] = {
+	[FW_ANA_AC_PROBE_PORT_CFG_PROBE_PORT_MASK] = 30,
+	[FW_ANA_AC_SRC_CFG_PORT_MASK] = 30,
+	[FW_ANA_AC_PGID_CFG_PORT_MASK] = 30,
+	[FW_ANA_AC_TSN_SF_PORT_NUM] = 7,
+	[FW_ANA_AC_TSN_SF_CFG_TSN_SGID] = 8,
+	[FW_ANA_AC_TSN_SF_STATUS_TSN_SFID] = 8,
+	[FW_ANA_AC_SG_ACCESS_CTRL_SGID] = 8,
+	[FW_ANA_AC_PORT_SGE_CFG_MASK] = 17,
+	[FW_ANA_AC_SDLB_XLB_START_LBSET_START] = 9,
+	[FW_ANA_AC_SDLB_LBGRP_MISC_THRES_SHIFT] = 3,
+	[FW_ANA_AC_SDLB_LBGRP_STATE_TBL_PUP_LBSET_NEXT] = 9,
+	[FW_ANA_AC_SDLB_XLB_NEXT_LBSET_NEXT] = 9,
+	[FW_ANA_AC_SDLB_XLB_NEXT_LBGRP] = 3,
+	[FW_ANA_AC_SDLB_INH_LBSET_ADDR_INH_LBSET_ADDR] = 9,
+	[FW_ANA_L2_AUTO_LRN_CFG_AUTO_LRN_ENA] = 30,
+	[FW_ANA_L2_DLB_CFG_DLB_IDX] = 9,
+	[FW_ANA_L2_TSN_CFG_TSN_SFID] = 8,
+	[FW_ANA_L3_VLAN_MASK_CFG_VLAN_PORT_MASK] = 30,
+	[FW_FDMA_CH_CFG_CH_DCB_DB_CNT] = 2,
+	[FW_GCB_HW_SGPIO_TO_SD_MAP_CFG_SGPIO_TO_SD_SEL] = 7,
+	[FW_HSCH_SE_CFG_SE_DWRR_CNT] = 5,
+	[FW_HSCH_SE_CONNECT_SE_LEAK_LINK] = 14,
+	[FW_HSCH_SE_DLB_SENSE_SE_DLB_DPORT] = 6,
+	[FW_HSCH_HSCH_CFG_CFG_CFG_SE_IDX] = 11,
+	[FW_HSCH_HSCH_LEAK_CFG_LEAK_FIRST] = 14,
+	[FW_HSCH_FLUSH_CTRL_FLUSH_PORT] = 6,
+	[FW_HSCH_FLUSH_CTRL_FLUSH_HIER] = 14,
+	[FW_LRN_COMMON_ACCESS_CTRL_CPU_ACCESS_DIRECT_ROW] = 13,
+	[FW_LRN_MAC_ACCESS_CFG_3_MAC_ENTRY_ISDX_LIMIT_IDX] = 8,
+	[FW_LRN_AUTOAGE_CFG_2_NEXT_ROW] = 13,
+	[FW_PTP_PTP_PIN_INTR_INTR_PTP] = 8,
+	[FW_PTP_PTP_PIN_INTR_ENA_INTR_PTP_ENA] = 8,
+	[FW_PTP_PTP_INTR_IDENT_INTR_PTP_IDENT] = 8,
+	[FW_PTP_PTP_PIN_CFG_PTP_PIN_SELECT] = 3,
+	[FW_QFWD_FRAME_COPY_CFG_FRMC_PORT_VAL] = 6,
+	[FW_QRES_RES_CFG_WM_HIGH] = 11,
+	[FW_QRES_RES_STAT_MAXUSE] = 19,
+	[FW_QRES_RES_STAT_CUR_INUSE] = 19,
+	[FW_QSYS_PAUSE_CFG_PAUSE_START] = 11,
+	[FW_QSYS_PAUSE_CFG_PAUSE_STOP] = 11,
+	[FW_QSYS_ATOP_ATOP] = 11,
+	[FW_QSYS_ATOP_TOT_CFG_ATOP_TOT] = 11,
+	[FW_REW_RTAG_ETAG_CTRL_IPE_TBL] = 6,
+	[FW_XQS_STAT_CFG_STAT_VIEW] = 10,
+	[FW_XQS_QLIMIT_SHR_TOP_CFG_QLIMIT_SHR_TOP] = 14,
+	[FW_XQS_QLIMIT_SHR_ATOP_CFG_QLIMIT_SHR_ATOP] = 14,
+	[FW_XQS_QLIMIT_SHR_CTOP_CFG_QLIMIT_SHR_CTOP] = 14,
+	[FW_XQS_QLIMIT_SHR_QLIM_CFG_QLIMIT_SHR_QLIM] = 14,
+};
--- /dev/null
+++ b/drivers/net/ethernet/microchip/sparx5/lan969x/lan969x_vcap_ag_api.c
@@ -0,0 +1,3843 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/* Copyright (C) 2024 Microchip Technology Inc. and its subsidiaries.
+ * Microchip VCAP API
+ */
+
+/* This file is autogenerated by cml-utils 2024-10-07 11:10:56 +0200.
+ * Commit ID: b5ddc8e244eb2481a9524f1ddc630a8b41e7c391
+ */
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+
+#include "lan969x.h"
+
+/* keyfields */
+static const struct vcap_field is0_normal_7tuple_keyfield[] = {
+	[VCAP_KF_TYPE] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 0,
+		.width = 1,
+	},
+	[VCAP_KF_LOOKUP_FIRST_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 1,
+		.width = 1,
+	},
+	[VCAP_KF_LOOKUP_GEN_IDX_SEL] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 2,
+		.width = 2,
+	},
+	[VCAP_KF_LOOKUP_GEN_IDX] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 4,
+		.width = 10,
+	},
+	[VCAP_KF_IF_IGR_PORT_MASK_SEL] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 14,
+		.width = 2,
+	},
+	[VCAP_KF_IF_IGR_PORT_MASK] = {
+		.type = VCAP_FIELD_U72,
+		.offset = 16,
+		.width = 65,
+	},
+	[VCAP_KF_L2_MC_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 81,
+		.width = 1,
+	},
+	[VCAP_KF_L2_BC_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 82,
+		.width = 1,
+	},
+	[VCAP_KF_8021Q_VLAN_TAGS] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 83,
+		.width = 3,
+	},
+	[VCAP_KF_8021Q_TPID0] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 86,
+		.width = 3,
+	},
+	[VCAP_KF_8021Q_PCP0] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 89,
+		.width = 3,
+	},
+	[VCAP_KF_8021Q_DEI0] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 92,
+		.width = 1,
+	},
+	[VCAP_KF_8021Q_VID0] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 93,
+		.width = 12,
+	},
+	[VCAP_KF_8021Q_TPID1] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 105,
+		.width = 3,
+	},
+	[VCAP_KF_8021Q_PCP1] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 108,
+		.width = 3,
+	},
+	[VCAP_KF_8021Q_DEI1] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 111,
+		.width = 1,
+	},
+	[VCAP_KF_8021Q_VID1] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 112,
+		.width = 12,
+	},
+	[VCAP_KF_8021Q_TPID2] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 124,
+		.width = 3,
+	},
+	[VCAP_KF_8021Q_PCP2] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 127,
+		.width = 3,
+	},
+	[VCAP_KF_8021Q_DEI2] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 130,
+		.width = 1,
+	},
+	[VCAP_KF_8021Q_VID2] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 131,
+		.width = 12,
+	},
+	[VCAP_KF_L2_DMAC] = {
+		.type = VCAP_FIELD_U48,
+		.offset = 144,
+		.width = 48,
+	},
+	[VCAP_KF_L2_SMAC] = {
+		.type = VCAP_FIELD_U48,
+		.offset = 192,
+		.width = 48,
+	},
+	[VCAP_KF_IP_MC_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 240,
+		.width = 1,
+	},
+	[VCAP_KF_ETYPE_LEN_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 241,
+		.width = 1,
+	},
+	[VCAP_KF_ETYPE] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 242,
+		.width = 16,
+	},
+	[VCAP_KF_IP_SNAP_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 258,
+		.width = 1,
+	},
+	[VCAP_KF_IP4_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 259,
+		.width = 1,
+	},
+	[VCAP_KF_L3_FRAGMENT_TYPE] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 260,
+		.width = 2,
+	},
+	[VCAP_KF_L3_FRAG_INVLD_L4_LEN] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 262,
+		.width = 1,
+	},
+	[VCAP_KF_L3_OPTIONS_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 263,
+		.width = 1,
+	},
+	[VCAP_KF_L3_DSCP] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 264,
+		.width = 6,
+	},
+	[VCAP_KF_L3_IP6_DIP] = {
+		.type = VCAP_FIELD_U128,
+		.offset = 270,
+		.width = 128,
+	},
+	[VCAP_KF_L3_IP6_SIP] = {
+		.type = VCAP_FIELD_U128,
+		.offset = 398,
+		.width = 128,
+	},
+	[VCAP_KF_TCP_UDP_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 526,
+		.width = 1,
+	},
+	[VCAP_KF_TCP_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 527,
+		.width = 1,
+	},
+	[VCAP_KF_L4_SPORT] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 528,
+		.width = 16,
+	},
+	[VCAP_KF_L4_RNG] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 544,
+		.width = 8,
+	},
+};
+
+static const struct vcap_field is0_normal_5tuple_ip4_keyfield[] = {
+	[VCAP_KF_TYPE] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 0,
+		.width = 2,
+	},
+	[VCAP_KF_LOOKUP_FIRST_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 2,
+		.width = 1,
+	},
+	[VCAP_KF_LOOKUP_GEN_IDX_SEL] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 3,
+		.width = 2,
+	},
+	[VCAP_KF_LOOKUP_GEN_IDX] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 5,
+		.width = 10,
+	},
+	[VCAP_KF_IF_IGR_PORT_MASK_SEL] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 15,
+		.width = 2,
+	},
+	[VCAP_KF_IF_IGR_PORT_MASK] = {
+		.type = VCAP_FIELD_U72,
+		.offset = 17,
+		.width = 65,
+	},
+	[VCAP_KF_L2_MC_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 82,
+		.width = 1,
+	},
+	[VCAP_KF_L2_BC_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 83,
+		.width = 1,
+	},
+	[VCAP_KF_8021Q_VLAN_TAGS] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 84,
+		.width = 3,
+	},
+	[VCAP_KF_8021Q_TPID0] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 87,
+		.width = 3,
+	},
+	[VCAP_KF_8021Q_PCP0] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 90,
+		.width = 3,
+	},
+	[VCAP_KF_8021Q_DEI0] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 93,
+		.width = 1,
+	},
+	[VCAP_KF_8021Q_VID0] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 94,
+		.width = 12,
+	},
+	[VCAP_KF_8021Q_TPID1] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 106,
+		.width = 3,
+	},
+	[VCAP_KF_8021Q_PCP1] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 109,
+		.width = 3,
+	},
+	[VCAP_KF_8021Q_DEI1] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 112,
+		.width = 1,
+	},
+	[VCAP_KF_8021Q_VID1] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 113,
+		.width = 12,
+	},
+	[VCAP_KF_8021Q_TPID2] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 125,
+		.width = 3,
+	},
+	[VCAP_KF_8021Q_PCP2] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 128,
+		.width = 3,
+	},
+	[VCAP_KF_8021Q_DEI2] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 131,
+		.width = 1,
+	},
+	[VCAP_KF_8021Q_VID2] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 132,
+		.width = 12,
+	},
+	[VCAP_KF_IP_MC_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 145,
+		.width = 1,
+	},
+	[VCAP_KF_IP4_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 146,
+		.width = 1,
+	},
+	[VCAP_KF_L3_FRAGMENT_TYPE] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 147,
+		.width = 2,
+	},
+	[VCAP_KF_L3_FRAG_INVLD_L4_LEN] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 149,
+		.width = 1,
+	},
+	[VCAP_KF_L3_OPTIONS_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 150,
+		.width = 1,
+	},
+	[VCAP_KF_L3_DSCP] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 151,
+		.width = 6,
+	},
+	[VCAP_KF_L3_IP4_DIP] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 157,
+		.width = 32,
+	},
+	[VCAP_KF_L3_IP4_SIP] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 189,
+		.width = 32,
+	},
+	[VCAP_KF_L3_IP_PROTO] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 221,
+		.width = 8,
+	},
+	[VCAP_KF_TCP_UDP_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 229,
+		.width = 1,
+	},
+	[VCAP_KF_TCP_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 230,
+		.width = 1,
+	},
+	[VCAP_KF_L4_RNG] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 231,
+		.width = 8,
+	},
+	[VCAP_KF_IP_PAYLOAD_5TUPLE] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 239,
+		.width = 32,
+	},
+};
+
+static const struct vcap_field is2_mac_etype_keyfield[] = {
+	[VCAP_KF_TYPE] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 0,
+		.width = 4,
+	},
+	[VCAP_KF_LOOKUP_FIRST_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 4,
+		.width = 1,
+	},
+	[VCAP_KF_LOOKUP_PAG] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 5,
+		.width = 8,
+	},
+	[VCAP_KF_IF_IGR_PORT_MASK_L3] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 13,
+		.width = 1,
+	},
+	[VCAP_KF_IF_IGR_PORT_MASK_RNG] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 14,
+		.width = 4,
+	},
+	[VCAP_KF_IF_IGR_PORT_MASK_SEL] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 18,
+		.width = 2,
+	},
+	[VCAP_KF_IF_IGR_PORT_MASK] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 20,
+		.width = 32,
+	},
+	[VCAP_KF_L2_MC_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 52,
+		.width = 1,
+	},
+	[VCAP_KF_L2_BC_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 53,
+		.width = 1,
+	},
+	[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 54,
+		.width = 1,
+	},
+	[VCAP_KF_ISDX_GT0_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 56,
+		.width = 1,
+	},
+	[VCAP_KF_ISDX_CLS] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 57,
+		.width = 10,
+	},
+	[VCAP_KF_8021Q_VID_CLS] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 67,
+		.width = 13,
+	},
+	[VCAP_KF_8021Q_DEI_CLS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 80,
+		.width = 1,
+	},
+	[VCAP_KF_8021Q_PCP_CLS] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 81,
+		.width = 3,
+	},
+	[VCAP_KF_L2_FWD_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 84,
+		.width = 1,
+	},
+	[VCAP_KF_L3_RT_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 87,
+		.width = 1,
+	},
+	[VCAP_KF_L3_DST_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 88,
+		.width = 1,
+	},
+	[VCAP_KF_L2_DMAC] = {
+		.type = VCAP_FIELD_U48,
+		.offset = 89,
+		.width = 48,
+	},
+	[VCAP_KF_L2_SMAC] = {
+		.type = VCAP_FIELD_U48,
+		.offset = 137,
+		.width = 48,
+	},
+	[VCAP_KF_ETYPE_LEN_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 185,
+		.width = 1,
+	},
+	[VCAP_KF_ETYPE] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 186,
+		.width = 16,
+	},
+	[VCAP_KF_L2_PAYLOAD_ETYPE] = {
+		.type = VCAP_FIELD_U64,
+		.offset = 202,
+		.width = 64,
+	},
+	[VCAP_KF_L4_RNG] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 266,
+		.width = 16,
+	},
+	[VCAP_KF_OAM_CCM_CNTS_EQ0] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 282,
+		.width = 1,
+	},
+	[VCAP_KF_OAM_Y1731_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 283,
+		.width = 1,
+	},
+};
+
+static const struct vcap_field is2_arp_keyfield[] = {
+	[VCAP_KF_TYPE] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 0,
+		.width = 4,
+	},
+	[VCAP_KF_LOOKUP_FIRST_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 4,
+		.width = 1,
+	},
+	[VCAP_KF_LOOKUP_PAG] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 5,
+		.width = 8,
+	},
+	[VCAP_KF_IF_IGR_PORT_MASK_L3] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 13,
+		.width = 1,
+	},
+	[VCAP_KF_IF_IGR_PORT_MASK_RNG] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 14,
+		.width = 4,
+	},
+	[VCAP_KF_IF_IGR_PORT_MASK_SEL] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 18,
+		.width = 2,
+	},
+	[VCAP_KF_IF_IGR_PORT_MASK] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 20,
+		.width = 32,
+	},
+	[VCAP_KF_L2_MC_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 52,
+		.width = 1,
+	},
+	[VCAP_KF_L2_BC_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 53,
+		.width = 1,
+	},
+	[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 54,
+		.width = 1,
+	},
+	[VCAP_KF_ISDX_GT0_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 56,
+		.width = 1,
+	},
+	[VCAP_KF_ISDX_CLS] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 57,
+		.width = 10,
+	},
+	[VCAP_KF_8021Q_VID_CLS] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 67,
+		.width = 13,
+	},
+	[VCAP_KF_8021Q_DEI_CLS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 80,
+		.width = 1,
+	},
+	[VCAP_KF_8021Q_PCP_CLS] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 81,
+		.width = 3,
+	},
+	[VCAP_KF_L2_FWD_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 84,
+		.width = 1,
+	},
+	[VCAP_KF_L2_SMAC] = {
+		.type = VCAP_FIELD_U48,
+		.offset = 85,
+		.width = 48,
+	},
+	[VCAP_KF_ARP_ADDR_SPACE_OK_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 133,
+		.width = 1,
+	},
+	[VCAP_KF_ARP_PROTO_SPACE_OK_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 134,
+		.width = 1,
+	},
+	[VCAP_KF_ARP_LEN_OK_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 135,
+		.width = 1,
+	},
+	[VCAP_KF_ARP_TGT_MATCH_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 136,
+		.width = 1,
+	},
+	[VCAP_KF_ARP_SENDER_MATCH_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 137,
+		.width = 1,
+	},
+	[VCAP_KF_ARP_OPCODE_UNKNOWN_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 138,
+		.width = 1,
+	},
+	[VCAP_KF_ARP_OPCODE] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 139,
+		.width = 2,
+	},
+	[VCAP_KF_L3_IP4_DIP] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 141,
+		.width = 32,
+	},
+	[VCAP_KF_L3_IP4_SIP] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 173,
+		.width = 32,
+	},
+	[VCAP_KF_L3_DIP_EQ_SIP_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 205,
+		.width = 1,
+	},
+	[VCAP_KF_L4_RNG] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 206,
+		.width = 16,
+	},
+};
+
+static const struct vcap_field is2_ip4_tcp_udp_keyfield[] = {
+	[VCAP_KF_TYPE] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 0,
+		.width = 4,
+	},
+	[VCAP_KF_LOOKUP_FIRST_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 4,
+		.width = 1,
+	},
+	[VCAP_KF_LOOKUP_PAG] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 5,
+		.width = 8,
+	},
+	[VCAP_KF_IF_IGR_PORT_MASK_L3] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 13,
+		.width = 1,
+	},
+	[VCAP_KF_IF_IGR_PORT_MASK_RNG] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 14,
+		.width = 4,
+	},
+	[VCAP_KF_IF_IGR_PORT_MASK_SEL] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 18,
+		.width = 2,
+	},
+	[VCAP_KF_IF_IGR_PORT_MASK] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 20,
+		.width = 32,
+	},
+	[VCAP_KF_L2_MC_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 52,
+		.width = 1,
+	},
+	[VCAP_KF_L2_BC_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 53,
+		.width = 1,
+	},
+	[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 54,
+		.width = 1,
+	},
+	[VCAP_KF_ISDX_GT0_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 56,
+		.width = 1,
+	},
+	[VCAP_KF_ISDX_CLS] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 57,
+		.width = 10,
+	},
+	[VCAP_KF_8021Q_VID_CLS] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 67,
+		.width = 13,
+	},
+	[VCAP_KF_8021Q_DEI_CLS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 80,
+		.width = 1,
+	},
+	[VCAP_KF_8021Q_PCP_CLS] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 81,
+		.width = 3,
+	},
+	[VCAP_KF_L2_FWD_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 84,
+		.width = 1,
+	},
+	[VCAP_KF_L3_RT_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 87,
+		.width = 1,
+	},
+	[VCAP_KF_L3_DST_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 88,
+		.width = 1,
+	},
+	[VCAP_KF_IP4_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 89,
+		.width = 1,
+	},
+	[VCAP_KF_L3_FRAGMENT_TYPE] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 90,
+		.width = 2,
+	},
+	[VCAP_KF_L3_FRAG_INVLD_L4_LEN] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 92,
+		.width = 1,
+	},
+	[VCAP_KF_L3_OPTIONS_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 93,
+		.width = 1,
+	},
+	[VCAP_KF_L3_TTL_GT0] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 94,
+		.width = 1,
+	},
+	[VCAP_KF_L3_TOS] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 95,
+		.width = 8,
+	},
+	[VCAP_KF_L3_IP4_DIP] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 103,
+		.width = 32,
+	},
+	[VCAP_KF_L3_IP4_SIP] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 135,
+		.width = 32,
+	},
+	[VCAP_KF_L3_DIP_EQ_SIP_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 167,
+		.width = 1,
+	},
+	[VCAP_KF_TCP_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 168,
+		.width = 1,
+	},
+	[VCAP_KF_L4_DPORT] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 169,
+		.width = 16,
+	},
+	[VCAP_KF_L4_SPORT] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 185,
+		.width = 16,
+	},
+	[VCAP_KF_L4_RNG] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 201,
+		.width = 16,
+	},
+	[VCAP_KF_L4_SPORT_EQ_DPORT_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 217,
+		.width = 1,
+	},
+	[VCAP_KF_L4_SEQUENCE_EQ0_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 218,
+		.width = 1,
+	},
+	[VCAP_KF_L4_FIN] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 219,
+		.width = 1,
+	},
+	[VCAP_KF_L4_SYN] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 220,
+		.width = 1,
+	},
+	[VCAP_KF_L4_RST] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 221,
+		.width = 1,
+	},
+	[VCAP_KF_L4_PSH] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 222,
+		.width = 1,
+	},
+	[VCAP_KF_L4_ACK] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 223,
+		.width = 1,
+	},
+	[VCAP_KF_L4_URG] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 224,
+		.width = 1,
+	},
+	[VCAP_KF_L4_PAYLOAD] = {
+		.type = VCAP_FIELD_U64,
+		.offset = 225,
+		.width = 64,
+	},
+};
+
+static const struct vcap_field is2_ip4_other_keyfield[] = {
+	[VCAP_KF_TYPE] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 0,
+		.width = 4,
+	},
+	[VCAP_KF_LOOKUP_FIRST_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 4,
+		.width = 1,
+	},
+	[VCAP_KF_LOOKUP_PAG] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 5,
+		.width = 8,
+	},
+	[VCAP_KF_IF_IGR_PORT_MASK_L3] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 13,
+		.width = 1,
+	},
+	[VCAP_KF_IF_IGR_PORT_MASK_RNG] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 14,
+		.width = 4,
+	},
+	[VCAP_KF_IF_IGR_PORT_MASK_SEL] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 18,
+		.width = 2,
+	},
+	[VCAP_KF_IF_IGR_PORT_MASK] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 20,
+		.width = 32,
+	},
+	[VCAP_KF_L2_MC_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 52,
+		.width = 1,
+	},
+	[VCAP_KF_L2_BC_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 53,
+		.width = 1,
+	},
+	[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 54,
+		.width = 1,
+	},
+	[VCAP_KF_ISDX_GT0_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 56,
+		.width = 1,
+	},
+	[VCAP_KF_ISDX_CLS] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 57,
+		.width = 10,
+	},
+	[VCAP_KF_8021Q_VID_CLS] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 67,
+		.width = 13,
+	},
+	[VCAP_KF_8021Q_DEI_CLS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 80,
+		.width = 1,
+	},
+	[VCAP_KF_8021Q_PCP_CLS] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 81,
+		.width = 3,
+	},
+	[VCAP_KF_L2_FWD_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 84,
+		.width = 1,
+	},
+	[VCAP_KF_L3_RT_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 87,
+		.width = 1,
+	},
+	[VCAP_KF_L3_DST_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 88,
+		.width = 1,
+	},
+	[VCAP_KF_IP4_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 89,
+		.width = 1,
+	},
+	[VCAP_KF_L3_FRAGMENT_TYPE] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 90,
+		.width = 2,
+	},
+	[VCAP_KF_L3_FRAG_INVLD_L4_LEN] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 92,
+		.width = 1,
+	},
+	[VCAP_KF_L3_OPTIONS_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 93,
+		.width = 1,
+	},
+	[VCAP_KF_L3_TTL_GT0] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 94,
+		.width = 1,
+	},
+	[VCAP_KF_L3_TOS] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 95,
+		.width = 8,
+	},
+	[VCAP_KF_L3_IP4_DIP] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 103,
+		.width = 32,
+	},
+	[VCAP_KF_L3_IP4_SIP] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 135,
+		.width = 32,
+	},
+	[VCAP_KF_L3_DIP_EQ_SIP_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 167,
+		.width = 1,
+	},
+	[VCAP_KF_L3_IP_PROTO] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 168,
+		.width = 8,
+	},
+	[VCAP_KF_L4_RNG] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 176,
+		.width = 16,
+	},
+	[VCAP_KF_L3_PAYLOAD] = {
+		.type = VCAP_FIELD_U112,
+		.offset = 192,
+		.width = 96,
+	},
+};
+
+static const struct vcap_field is2_ip6_std_keyfield[] = {
+	[VCAP_KF_TYPE] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 0,
+		.width = 4,
+	},
+	[VCAP_KF_LOOKUP_FIRST_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 4,
+		.width = 1,
+	},
+	[VCAP_KF_LOOKUP_PAG] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 5,
+		.width = 8,
+	},
+	[VCAP_KF_IF_IGR_PORT_MASK_L3] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 13,
+		.width = 1,
+	},
+	[VCAP_KF_IF_IGR_PORT_MASK_RNG] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 14,
+		.width = 4,
+	},
+	[VCAP_KF_IF_IGR_PORT_MASK_SEL] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 18,
+		.width = 2,
+	},
+	[VCAP_KF_IF_IGR_PORT_MASK] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 20,
+		.width = 32,
+	},
+	[VCAP_KF_L2_MC_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 52,
+		.width = 1,
+	},
+	[VCAP_KF_L2_BC_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 53,
+		.width = 1,
+	},
+	[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 54,
+		.width = 1,
+	},
+	[VCAP_KF_ISDX_GT0_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 56,
+		.width = 1,
+	},
+	[VCAP_KF_ISDX_CLS] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 57,
+		.width = 10,
+	},
+	[VCAP_KF_8021Q_VID_CLS] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 67,
+		.width = 13,
+	},
+	[VCAP_KF_8021Q_DEI_CLS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 80,
+		.width = 1,
+	},
+	[VCAP_KF_8021Q_PCP_CLS] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 81,
+		.width = 3,
+	},
+	[VCAP_KF_L2_FWD_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 84,
+		.width = 1,
+	},
+	[VCAP_KF_L3_RT_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 87,
+		.width = 1,
+	},
+	[VCAP_KF_L3_TTL_GT0] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 89,
+		.width = 1,
+	},
+	[VCAP_KF_L3_IP6_SIP] = {
+		.type = VCAP_FIELD_U128,
+		.offset = 90,
+		.width = 128,
+	},
+	[VCAP_KF_L3_DIP_EQ_SIP_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 218,
+		.width = 1,
+	},
+	[VCAP_KF_L3_IP_PROTO] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 219,
+		.width = 8,
+	},
+	[VCAP_KF_L4_RNG] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 227,
+		.width = 16,
+	},
+	[VCAP_KF_L3_PAYLOAD] = {
+		.type = VCAP_FIELD_U48,
+		.offset = 243,
+		.width = 40,
+	},
+};
+
+static const struct vcap_field is2_ip_7tuple_keyfield[] = {
+	[VCAP_KF_TYPE] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 0,
+		.width = 2,
+	},
+	[VCAP_KF_LOOKUP_FIRST_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 2,
+		.width = 1,
+	},
+	[VCAP_KF_LOOKUP_PAG] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 3,
+		.width = 8,
+	},
+	[VCAP_KF_IF_IGR_PORT_MASK_L3] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 11,
+		.width = 1,
+	},
+	[VCAP_KF_IF_IGR_PORT_MASK_RNG] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 12,
+		.width = 4,
+	},
+	[VCAP_KF_IF_IGR_PORT_MASK_SEL] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 16,
+		.width = 2,
+	},
+	[VCAP_KF_IF_IGR_PORT_MASK] = {
+		.type = VCAP_FIELD_U72,
+		.offset = 18,
+		.width = 65,
+	},
+	[VCAP_KF_L2_MC_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 83,
+		.width = 1,
+	},
+	[VCAP_KF_L2_BC_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 84,
+		.width = 1,
+	},
+	[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 85,
+		.width = 1,
+	},
+	[VCAP_KF_ISDX_GT0_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 87,
+		.width = 1,
+	},
+	[VCAP_KF_ISDX_CLS] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 88,
+		.width = 10,
+	},
+	[VCAP_KF_8021Q_VID_CLS] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 98,
+		.width = 13,
+	},
+	[VCAP_KF_8021Q_DEI_CLS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 111,
+		.width = 1,
+	},
+	[VCAP_KF_8021Q_PCP_CLS] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 112,
+		.width = 3,
+	},
+	[VCAP_KF_L2_FWD_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 115,
+		.width = 1,
+	},
+	[VCAP_KF_L3_RT_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 118,
+		.width = 1,
+	},
+	[VCAP_KF_L3_DST_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 119,
+		.width = 1,
+	},
+	[VCAP_KF_L2_DMAC] = {
+		.type = VCAP_FIELD_U48,
+		.offset = 120,
+		.width = 48,
+	},
+	[VCAP_KF_L2_SMAC] = {
+		.type = VCAP_FIELD_U48,
+		.offset = 168,
+		.width = 48,
+	},
+	[VCAP_KF_IP4_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 218,
+		.width = 1,
+	},
+	[VCAP_KF_L3_TTL_GT0] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 219,
+		.width = 1,
+	},
+	[VCAP_KF_L3_TOS] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 220,
+		.width = 8,
+	},
+	[VCAP_KF_L3_IP6_DIP] = {
+		.type = VCAP_FIELD_U128,
+		.offset = 228,
+		.width = 128,
+	},
+	[VCAP_KF_L3_IP6_SIP] = {
+		.type = VCAP_FIELD_U128,
+		.offset = 356,
+		.width = 128,
+	},
+	[VCAP_KF_L3_DIP_EQ_SIP_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 484,
+		.width = 1,
+	},
+	[VCAP_KF_TCP_UDP_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 485,
+		.width = 1,
+	},
+	[VCAP_KF_TCP_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 486,
+		.width = 1,
+	},
+	[VCAP_KF_L4_DPORT] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 487,
+		.width = 16,
+	},
+	[VCAP_KF_L4_SPORT] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 503,
+		.width = 16,
+	},
+	[VCAP_KF_L4_RNG] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 519,
+		.width = 16,
+	},
+	[VCAP_KF_L4_SPORT_EQ_DPORT_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 535,
+		.width = 1,
+	},
+	[VCAP_KF_L4_SEQUENCE_EQ0_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 536,
+		.width = 1,
+	},
+	[VCAP_KF_L4_FIN] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 537,
+		.width = 1,
+	},
+	[VCAP_KF_L4_SYN] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 538,
+		.width = 1,
+	},
+	[VCAP_KF_L4_RST] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 539,
+		.width = 1,
+	},
+	[VCAP_KF_L4_PSH] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 540,
+		.width = 1,
+	},
+	[VCAP_KF_L4_ACK] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 541,
+		.width = 1,
+	},
+	[VCAP_KF_L4_URG] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 542,
+		.width = 1,
+	},
+	[VCAP_KF_L4_PAYLOAD] = {
+		.type = VCAP_FIELD_U64,
+		.offset = 543,
+		.width = 64,
+	},
+};
+
+static const struct vcap_field es0_isdx_keyfield[] = {
+	[VCAP_KF_TYPE] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 0,
+		.width = 1,
+	},
+	[VCAP_KF_IF_EGR_PORT_NO] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 1,
+		.width = 6,
+	},
+	[VCAP_KF_8021Q_VID_CLS] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 7,
+		.width = 13,
+	},
+	[VCAP_KF_COSID_CLS] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 20,
+		.width = 3,
+	},
+	[VCAP_KF_8021Q_TPID] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 23,
+		.width = 3,
+	},
+	[VCAP_KF_L3_DPL_CLS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 26,
+		.width = 1,
+	},
+	[VCAP_KF_ISDX_GT0_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 27,
+		.width = 1,
+	},
+	[VCAP_KF_PROT_ACTIVE] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 28,
+		.width = 1,
+	},
+	[VCAP_KF_ISDX_CLS] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 38,
+		.width = 10,
+	},
+};
+
+static const struct vcap_field es2_mac_etype_keyfield[] = {
+	[VCAP_KF_TYPE] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 0,
+		.width = 3,
+	},
+	[VCAP_KF_LOOKUP_FIRST_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 3,
+		.width = 1,
+	},
+	[VCAP_KF_L2_MC_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 13,
+		.width = 1,
+	},
+	[VCAP_KF_L2_BC_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 14,
+		.width = 1,
+	},
+	[VCAP_KF_ISDX_GT0_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 15,
+		.width = 1,
+	},
+	[VCAP_KF_ISDX_CLS] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 16,
+		.width = 10,
+	},
+	[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 26,
+		.width = 1,
+	},
+	[VCAP_KF_8021Q_VID_CLS] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 28,
+		.width = 13,
+	},
+	[VCAP_KF_IF_EGR_PORT_MASK_RNG] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 41,
+		.width = 3,
+	},
+	[VCAP_KF_IF_EGR_PORT_MASK] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 44,
+		.width = 32,
+	},
+	[VCAP_KF_IF_IGR_PORT_SEL] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 76,
+		.width = 1,
+	},
+	[VCAP_KF_IF_IGR_PORT] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 77,
+		.width = 7,
+	},
+	[VCAP_KF_8021Q_PCP_CLS] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 84,
+		.width = 3,
+	},
+	[VCAP_KF_8021Q_DEI_CLS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 87,
+		.width = 1,
+	},
+	[VCAP_KF_COSID_CLS] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 88,
+		.width = 3,
+	},
+	[VCAP_KF_L3_DPL_CLS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 91,
+		.width = 1,
+	},
+	[VCAP_KF_L3_RT_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 92,
+		.width = 1,
+	},
+	[VCAP_KF_L2_DMAC] = {
+		.type = VCAP_FIELD_U48,
+		.offset = 96,
+		.width = 48,
+	},
+	[VCAP_KF_L2_SMAC] = {
+		.type = VCAP_FIELD_U48,
+		.offset = 144,
+		.width = 48,
+	},
+	[VCAP_KF_ETYPE_LEN_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 192,
+		.width = 1,
+	},
+	[VCAP_KF_ETYPE] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 193,
+		.width = 16,
+	},
+	[VCAP_KF_L2_PAYLOAD_ETYPE] = {
+		.type = VCAP_FIELD_U64,
+		.offset = 209,
+		.width = 64,
+	},
+	[VCAP_KF_OAM_CCM_CNTS_EQ0] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 273,
+		.width = 1,
+	},
+	[VCAP_KF_OAM_Y1731_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 274,
+		.width = 1,
+	},
+};
+
+static const struct vcap_field es2_arp_keyfield[] = {
+	[VCAP_KF_TYPE] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 0,
+		.width = 3,
+	},
+	[VCAP_KF_LOOKUP_FIRST_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 3,
+		.width = 1,
+	},
+	[VCAP_KF_L2_MC_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 13,
+		.width = 1,
+	},
+	[VCAP_KF_L2_BC_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 14,
+		.width = 1,
+	},
+	[VCAP_KF_ISDX_GT0_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 15,
+		.width = 1,
+	},
+	[VCAP_KF_ISDX_CLS] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 16,
+		.width = 10,
+	},
+	[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 26,
+		.width = 1,
+	},
+	[VCAP_KF_8021Q_VID_CLS] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 28,
+		.width = 13,
+	},
+	[VCAP_KF_IF_EGR_PORT_MASK_RNG] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 41,
+		.width = 3,
+	},
+	[VCAP_KF_IF_EGR_PORT_MASK] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 44,
+		.width = 32,
+	},
+	[VCAP_KF_IF_IGR_PORT_SEL] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 76,
+		.width = 1,
+	},
+	[VCAP_KF_IF_IGR_PORT] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 77,
+		.width = 7,
+	},
+	[VCAP_KF_8021Q_PCP_CLS] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 84,
+		.width = 3,
+	},
+	[VCAP_KF_8021Q_DEI_CLS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 87,
+		.width = 1,
+	},
+	[VCAP_KF_COSID_CLS] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 88,
+		.width = 3,
+	},
+	[VCAP_KF_L3_DPL_CLS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 91,
+		.width = 1,
+	},
+	[VCAP_KF_L2_SMAC] = {
+		.type = VCAP_FIELD_U48,
+		.offset = 95,
+		.width = 48,
+	},
+	[VCAP_KF_ARP_ADDR_SPACE_OK_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 143,
+		.width = 1,
+	},
+	[VCAP_KF_ARP_PROTO_SPACE_OK_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 144,
+		.width = 1,
+	},
+	[VCAP_KF_ARP_LEN_OK_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 145,
+		.width = 1,
+	},
+	[VCAP_KF_ARP_TGT_MATCH_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 146,
+		.width = 1,
+	},
+	[VCAP_KF_ARP_SENDER_MATCH_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 147,
+		.width = 1,
+	},
+	[VCAP_KF_ARP_OPCODE_UNKNOWN_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 148,
+		.width = 1,
+	},
+	[VCAP_KF_ARP_OPCODE] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 149,
+		.width = 2,
+	},
+	[VCAP_KF_L3_IP4_DIP] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 151,
+		.width = 32,
+	},
+	[VCAP_KF_L3_IP4_SIP] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 183,
+		.width = 32,
+	},
+	[VCAP_KF_L3_DIP_EQ_SIP_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 215,
+		.width = 1,
+	},
+};
+
+static const struct vcap_field es2_ip4_tcp_udp_keyfield[] = {
+	[VCAP_KF_TYPE] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 0,
+		.width = 3,
+	},
+	[VCAP_KF_LOOKUP_FIRST_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 3,
+		.width = 1,
+	},
+	[VCAP_KF_L2_MC_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 13,
+		.width = 1,
+	},
+	[VCAP_KF_L2_BC_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 14,
+		.width = 1,
+	},
+	[VCAP_KF_ISDX_GT0_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 15,
+		.width = 1,
+	},
+	[VCAP_KF_ISDX_CLS] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 16,
+		.width = 10,
+	},
+	[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 26,
+		.width = 1,
+	},
+	[VCAP_KF_8021Q_VID_CLS] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 28,
+		.width = 13,
+	},
+	[VCAP_KF_IF_EGR_PORT_MASK_RNG] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 41,
+		.width = 3,
+	},
+	[VCAP_KF_IF_EGR_PORT_MASK] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 44,
+		.width = 32,
+	},
+	[VCAP_KF_IF_IGR_PORT_SEL] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 76,
+		.width = 1,
+	},
+	[VCAP_KF_IF_IGR_PORT] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 77,
+		.width = 7,
+	},
+	[VCAP_KF_8021Q_PCP_CLS] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 84,
+		.width = 3,
+	},
+	[VCAP_KF_8021Q_DEI_CLS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 87,
+		.width = 1,
+	},
+	[VCAP_KF_COSID_CLS] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 88,
+		.width = 3,
+	},
+	[VCAP_KF_L3_DPL_CLS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 91,
+		.width = 1,
+	},
+	[VCAP_KF_L3_RT_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 92,
+		.width = 1,
+	},
+	[VCAP_KF_IP4_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 96,
+		.width = 1,
+	},
+	[VCAP_KF_L3_FRAGMENT_TYPE] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 97,
+		.width = 2,
+	},
+	[VCAP_KF_L3_OPTIONS_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 99,
+		.width = 1,
+	},
+	[VCAP_KF_L3_TTL_GT0] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 100,
+		.width = 1,
+	},
+	[VCAP_KF_L3_TOS] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 101,
+		.width = 8,
+	},
+	[VCAP_KF_L3_IP4_DIP] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 109,
+		.width = 32,
+	},
+	[VCAP_KF_L3_IP4_SIP] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 141,
+		.width = 32,
+	},
+	[VCAP_KF_L3_DIP_EQ_SIP_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 173,
+		.width = 1,
+	},
+	[VCAP_KF_TCP_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 174,
+		.width = 1,
+	},
+	[VCAP_KF_L4_DPORT] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 175,
+		.width = 16,
+	},
+	[VCAP_KF_L4_SPORT] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 191,
+		.width = 16,
+	},
+	[VCAP_KF_L4_RNG] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 207,
+		.width = 16,
+	},
+	[VCAP_KF_L4_SPORT_EQ_DPORT_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 223,
+		.width = 1,
+	},
+	[VCAP_KF_L4_SEQUENCE_EQ0_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 224,
+		.width = 1,
+	},
+	[VCAP_KF_L4_FIN] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 225,
+		.width = 1,
+	},
+	[VCAP_KF_L4_SYN] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 226,
+		.width = 1,
+	},
+	[VCAP_KF_L4_RST] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 227,
+		.width = 1,
+	},
+	[VCAP_KF_L4_PSH] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 228,
+		.width = 1,
+	},
+	[VCAP_KF_L4_ACK] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 229,
+		.width = 1,
+	},
+	[VCAP_KF_L4_URG] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 230,
+		.width = 1,
+	},
+	[VCAP_KF_L4_PAYLOAD] = {
+		.type = VCAP_FIELD_U64,
+		.offset = 231,
+		.width = 64,
+	},
+};
+
+static const struct vcap_field es2_ip4_other_keyfield[] = {
+	[VCAP_KF_TYPE] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 0,
+		.width = 3,
+	},
+	[VCAP_KF_LOOKUP_FIRST_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 3,
+		.width = 1,
+	},
+	[VCAP_KF_L2_MC_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 13,
+		.width = 1,
+	},
+	[VCAP_KF_L2_BC_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 14,
+		.width = 1,
+	},
+	[VCAP_KF_ISDX_GT0_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 15,
+		.width = 1,
+	},
+	[VCAP_KF_ISDX_CLS] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 16,
+		.width = 10,
+	},
+	[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 26,
+		.width = 1,
+	},
+	[VCAP_KF_8021Q_VID_CLS] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 28,
+		.width = 13,
+	},
+	[VCAP_KF_IF_EGR_PORT_MASK_RNG] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 41,
+		.width = 3,
+	},
+	[VCAP_KF_IF_EGR_PORT_MASK] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 44,
+		.width = 32,
+	},
+	[VCAP_KF_IF_IGR_PORT_SEL] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 76,
+		.width = 1,
+	},
+	[VCAP_KF_IF_IGR_PORT] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 77,
+		.width = 7,
+	},
+	[VCAP_KF_8021Q_PCP_CLS] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 84,
+		.width = 3,
+	},
+	[VCAP_KF_8021Q_DEI_CLS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 87,
+		.width = 1,
+	},
+	[VCAP_KF_COSID_CLS] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 88,
+		.width = 3,
+	},
+	[VCAP_KF_L3_DPL_CLS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 91,
+		.width = 1,
+	},
+	[VCAP_KF_L3_RT_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 92,
+		.width = 1,
+	},
+	[VCAP_KF_IP4_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 96,
+		.width = 1,
+	},
+	[VCAP_KF_L3_FRAGMENT_TYPE] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 97,
+		.width = 2,
+	},
+	[VCAP_KF_L3_OPTIONS_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 99,
+		.width = 1,
+	},
+	[VCAP_KF_L3_TTL_GT0] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 100,
+		.width = 1,
+	},
+	[VCAP_KF_L3_TOS] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 101,
+		.width = 8,
+	},
+	[VCAP_KF_L3_IP4_DIP] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 109,
+		.width = 32,
+	},
+	[VCAP_KF_L3_IP4_SIP] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 141,
+		.width = 32,
+	},
+	[VCAP_KF_L3_DIP_EQ_SIP_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 173,
+		.width = 1,
+	},
+	[VCAP_KF_L3_IP_PROTO] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 174,
+		.width = 8,
+	},
+	[VCAP_KF_L3_PAYLOAD] = {
+		.type = VCAP_FIELD_U112,
+		.offset = 182,
+		.width = 96,
+	},
+};
+
+static const struct vcap_field es2_ip_7tuple_keyfield[] = {
+	[VCAP_KF_LOOKUP_FIRST_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 0,
+		.width = 1,
+	},
+	[VCAP_KF_L2_MC_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 10,
+		.width = 1,
+	},
+	[VCAP_KF_L2_BC_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 11,
+		.width = 1,
+	},
+	[VCAP_KF_ISDX_GT0_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 12,
+		.width = 1,
+	},
+	[VCAP_KF_ISDX_CLS] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 13,
+		.width = 10,
+	},
+	[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 23,
+		.width = 1,
+	},
+	[VCAP_KF_8021Q_VID_CLS] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 25,
+		.width = 13,
+	},
+	[VCAP_KF_IF_EGR_PORT_MASK_RNG] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 38,
+		.width = 3,
+	},
+	[VCAP_KF_IF_EGR_PORT_MASK] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 41,
+		.width = 32,
+	},
+	[VCAP_KF_IF_IGR_PORT_SEL] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 73,
+		.width = 1,
+	},
+	[VCAP_KF_IF_IGR_PORT] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 74,
+		.width = 7,
+	},
+	[VCAP_KF_8021Q_PCP_CLS] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 81,
+		.width = 3,
+	},
+	[VCAP_KF_8021Q_DEI_CLS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 84,
+		.width = 1,
+	},
+	[VCAP_KF_COSID_CLS] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 85,
+		.width = 3,
+	},
+	[VCAP_KF_L3_DPL_CLS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 88,
+		.width = 1,
+	},
+	[VCAP_KF_L3_RT_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 89,
+		.width = 1,
+	},
+	[VCAP_KF_L2_DMAC] = {
+		.type = VCAP_FIELD_U48,
+		.offset = 93,
+		.width = 48,
+	},
+	[VCAP_KF_L2_SMAC] = {
+		.type = VCAP_FIELD_U48,
+		.offset = 141,
+		.width = 48,
+	},
+	[VCAP_KF_IP4_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 191,
+		.width = 1,
+	},
+	[VCAP_KF_L3_TTL_GT0] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 192,
+		.width = 1,
+	},
+	[VCAP_KF_L3_TOS] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 193,
+		.width = 8,
+	},
+	[VCAP_KF_L3_IP6_DIP] = {
+		.type = VCAP_FIELD_U128,
+		.offset = 201,
+		.width = 128,
+	},
+	[VCAP_KF_L3_IP6_SIP] = {
+		.type = VCAP_FIELD_U128,
+		.offset = 329,
+		.width = 128,
+	},
+	[VCAP_KF_L3_DIP_EQ_SIP_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 457,
+		.width = 1,
+	},
+	[VCAP_KF_TCP_UDP_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 458,
+		.width = 1,
+	},
+	[VCAP_KF_TCP_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 459,
+		.width = 1,
+	},
+	[VCAP_KF_L4_DPORT] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 460,
+		.width = 16,
+	},
+	[VCAP_KF_L4_SPORT] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 476,
+		.width = 16,
+	},
+	[VCAP_KF_L4_RNG] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 492,
+		.width = 16,
+	},
+	[VCAP_KF_L4_SPORT_EQ_DPORT_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 508,
+		.width = 1,
+	},
+	[VCAP_KF_L4_SEQUENCE_EQ0_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 509,
+		.width = 1,
+	},
+	[VCAP_KF_L4_FIN] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 510,
+		.width = 1,
+	},
+	[VCAP_KF_L4_SYN] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 511,
+		.width = 1,
+	},
+	[VCAP_KF_L4_RST] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 512,
+		.width = 1,
+	},
+	[VCAP_KF_L4_PSH] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 513,
+		.width = 1,
+	},
+	[VCAP_KF_L4_ACK] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 514,
+		.width = 1,
+	},
+	[VCAP_KF_L4_URG] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 515,
+		.width = 1,
+	},
+	[VCAP_KF_L4_PAYLOAD] = {
+		.type = VCAP_FIELD_U64,
+		.offset = 516,
+		.width = 64,
+	},
+};
+
+static const struct vcap_field es2_ip6_std_keyfield[] = {
+	[VCAP_KF_TYPE] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 0,
+		.width = 3,
+	},
+	[VCAP_KF_LOOKUP_FIRST_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 3,
+		.width = 1,
+	},
+	[VCAP_KF_L2_MC_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 13,
+		.width = 1,
+	},
+	[VCAP_KF_L2_BC_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 14,
+		.width = 1,
+	},
+	[VCAP_KF_ISDX_GT0_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 15,
+		.width = 1,
+	},
+	[VCAP_KF_ISDX_CLS] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 16,
+		.width = 10,
+	},
+	[VCAP_KF_8021Q_VLAN_TAGGED_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 26,
+		.width = 1,
+	},
+	[VCAP_KF_8021Q_VID_CLS] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 28,
+		.width = 13,
+	},
+	[VCAP_KF_IF_EGR_PORT_MASK_RNG] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 41,
+		.width = 3,
+	},
+	[VCAP_KF_IF_EGR_PORT_MASK] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 44,
+		.width = 32,
+	},
+	[VCAP_KF_IF_IGR_PORT_SEL] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 76,
+		.width = 1,
+	},
+	[VCAP_KF_IF_IGR_PORT] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 77,
+		.width = 7,
+	},
+	[VCAP_KF_8021Q_PCP_CLS] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 84,
+		.width = 3,
+	},
+	[VCAP_KF_8021Q_DEI_CLS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 87,
+		.width = 1,
+	},
+	[VCAP_KF_COSID_CLS] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 88,
+		.width = 3,
+	},
+	[VCAP_KF_L3_DPL_CLS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 91,
+		.width = 1,
+	},
+	[VCAP_KF_L3_RT_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 92,
+		.width = 1,
+	},
+	[VCAP_KF_L3_TTL_GT0] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 96,
+		.width = 1,
+	},
+	[VCAP_KF_L3_IP6_SIP] = {
+		.type = VCAP_FIELD_U128,
+		.offset = 97,
+		.width = 128,
+	},
+	[VCAP_KF_L3_DIP_EQ_SIP_IS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 225,
+		.width = 1,
+	},
+	[VCAP_KF_L3_IP_PROTO] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 226,
+		.width = 8,
+	},
+	[VCAP_KF_L4_RNG] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 234,
+		.width = 16,
+	},
+	[VCAP_KF_L3_PAYLOAD] = {
+		.type = VCAP_FIELD_U48,
+		.offset = 250,
+		.width = 40,
+	},
+};
+
+/* keyfield_set */
+static const struct vcap_set is0_keyfield_set[] = {
+	[VCAP_KFS_NORMAL_7TUPLE] = {
+		.type_id = 0,
+		.sw_per_item = 12,
+		.sw_cnt = 1,
+	},
+	[VCAP_KFS_NORMAL_5TUPLE_IP4] = {
+		.type_id = 2,
+		.sw_per_item = 6,
+		.sw_cnt = 2,
+	},
+};
+
+static const struct vcap_set is2_keyfield_set[] = {
+	[VCAP_KFS_MAC_ETYPE] = {
+		.type_id = 0,
+		.sw_per_item = 6,
+		.sw_cnt = 2,
+	},
+	[VCAP_KFS_ARP] = {
+		.type_id = 3,
+		.sw_per_item = 6,
+		.sw_cnt = 2,
+	},
+	[VCAP_KFS_IP4_TCP_UDP] = {
+		.type_id = 4,
+		.sw_per_item = 6,
+		.sw_cnt = 2,
+	},
+	[VCAP_KFS_IP4_OTHER] = {
+		.type_id = 5,
+		.sw_per_item = 6,
+		.sw_cnt = 2,
+	},
+	[VCAP_KFS_IP6_STD] = {
+		.type_id = 6,
+		.sw_per_item = 6,
+		.sw_cnt = 2,
+	},
+	[VCAP_KFS_IP_7TUPLE] = {
+		.type_id = 1,
+		.sw_per_item = 12,
+		.sw_cnt = 1,
+	},
+};
+
+static const struct vcap_set es0_keyfield_set[] = {
+	[VCAP_KFS_ISDX] = {
+		.type_id = 0,
+		.sw_per_item = 1,
+		.sw_cnt = 1,
+	},
+};
+
+static const struct vcap_set es2_keyfield_set[] = {
+	[VCAP_KFS_MAC_ETYPE] = {
+		.type_id = 0,
+		.sw_per_item = 6,
+		.sw_cnt = 2,
+	},
+	[VCAP_KFS_ARP] = {
+		.type_id = 1,
+		.sw_per_item = 6,
+		.sw_cnt = 2,
+	},
+	[VCAP_KFS_IP4_TCP_UDP] = {
+		.type_id = 2,
+		.sw_per_item = 6,
+		.sw_cnt = 2,
+	},
+	[VCAP_KFS_IP4_OTHER] = {
+		.type_id = 3,
+		.sw_per_item = 6,
+		.sw_cnt = 2,
+	},
+	[VCAP_KFS_IP_7TUPLE] = {
+		.type_id = -1,
+		.sw_per_item = 12,
+		.sw_cnt = 1,
+	},
+	[VCAP_KFS_IP6_STD] = {
+		.type_id = 4,
+		.sw_per_item = 6,
+		.sw_cnt = 2,
+	},
+};
+
+/* keyfield_set map */
+static const struct vcap_field *is0_keyfield_set_map[] = {
+	[VCAP_KFS_NORMAL_7TUPLE] = is0_normal_7tuple_keyfield,
+	[VCAP_KFS_NORMAL_5TUPLE_IP4] = is0_normal_5tuple_ip4_keyfield,
+};
+
+static const struct vcap_field *is2_keyfield_set_map[] = {
+	[VCAP_KFS_MAC_ETYPE] = is2_mac_etype_keyfield,
+	[VCAP_KFS_ARP] = is2_arp_keyfield,
+	[VCAP_KFS_IP4_TCP_UDP] = is2_ip4_tcp_udp_keyfield,
+	[VCAP_KFS_IP4_OTHER] = is2_ip4_other_keyfield,
+	[VCAP_KFS_IP6_STD] = is2_ip6_std_keyfield,
+	[VCAP_KFS_IP_7TUPLE] = is2_ip_7tuple_keyfield,
+};
+
+static const struct vcap_field *es0_keyfield_set_map[] = {
+	[VCAP_KFS_ISDX] = es0_isdx_keyfield,
+};
+
+static const struct vcap_field *es2_keyfield_set_map[] = {
+	[VCAP_KFS_MAC_ETYPE] = es2_mac_etype_keyfield,
+	[VCAP_KFS_ARP] = es2_arp_keyfield,
+	[VCAP_KFS_IP4_TCP_UDP] = es2_ip4_tcp_udp_keyfield,
+	[VCAP_KFS_IP4_OTHER] = es2_ip4_other_keyfield,
+	[VCAP_KFS_IP_7TUPLE] = es2_ip_7tuple_keyfield,
+	[VCAP_KFS_IP6_STD] = es2_ip6_std_keyfield,
+};
+
+/* keyfield_set map sizes */
+static int is0_keyfield_set_map_size[] = {
+	[VCAP_KFS_NORMAL_7TUPLE] = ARRAY_SIZE(is0_normal_7tuple_keyfield),
+	[VCAP_KFS_NORMAL_5TUPLE_IP4] = ARRAY_SIZE(is0_normal_5tuple_ip4_keyfield),
+};
+
+static int is2_keyfield_set_map_size[] = {
+	[VCAP_KFS_MAC_ETYPE] = ARRAY_SIZE(is2_mac_etype_keyfield),
+	[VCAP_KFS_ARP] = ARRAY_SIZE(is2_arp_keyfield),
+	[VCAP_KFS_IP4_TCP_UDP] = ARRAY_SIZE(is2_ip4_tcp_udp_keyfield),
+	[VCAP_KFS_IP4_OTHER] = ARRAY_SIZE(is2_ip4_other_keyfield),
+	[VCAP_KFS_IP6_STD] = ARRAY_SIZE(is2_ip6_std_keyfield),
+	[VCAP_KFS_IP_7TUPLE] = ARRAY_SIZE(is2_ip_7tuple_keyfield),
+};
+
+static int es0_keyfield_set_map_size[] = {
+	[VCAP_KFS_ISDX] = ARRAY_SIZE(es0_isdx_keyfield),
+};
+
+static int es2_keyfield_set_map_size[] = {
+	[VCAP_KFS_MAC_ETYPE] = ARRAY_SIZE(es2_mac_etype_keyfield),
+	[VCAP_KFS_ARP] = ARRAY_SIZE(es2_arp_keyfield),
+	[VCAP_KFS_IP4_TCP_UDP] = ARRAY_SIZE(es2_ip4_tcp_udp_keyfield),
+	[VCAP_KFS_IP4_OTHER] = ARRAY_SIZE(es2_ip4_other_keyfield),
+	[VCAP_KFS_IP_7TUPLE] = ARRAY_SIZE(es2_ip_7tuple_keyfield),
+	[VCAP_KFS_IP6_STD] = ARRAY_SIZE(es2_ip6_std_keyfield),
+};
+
+/* actionfields */
+static const struct vcap_field is0_classification_actionfield[] = {
+	[VCAP_AF_TYPE] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 0,
+		.width = 1,
+	},
+	[VCAP_AF_DSCP_ENA] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 1,
+		.width = 1,
+	},
+	[VCAP_AF_DSCP_VAL] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 2,
+		.width = 6,
+	},
+	[VCAP_AF_QOS_ENA] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 12,
+		.width = 1,
+	},
+	[VCAP_AF_QOS_VAL] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 13,
+		.width = 3,
+	},
+	[VCAP_AF_DP_ENA] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 16,
+		.width = 1,
+	},
+	[VCAP_AF_DP_VAL] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 17,
+		.width = 2,
+	},
+	[VCAP_AF_DEI_ENA] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 19,
+		.width = 1,
+	},
+	[VCAP_AF_DEI_VAL] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 20,
+		.width = 1,
+	},
+	[VCAP_AF_PCP_ENA] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 21,
+		.width = 1,
+	},
+	[VCAP_AF_PCP_VAL] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 22,
+		.width = 3,
+	},
+	[VCAP_AF_MAP_LOOKUP_SEL] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 25,
+		.width = 2,
+	},
+	[VCAP_AF_MAP_KEY] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 27,
+		.width = 3,
+	},
+	[VCAP_AF_MAP_IDX] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 30,
+		.width = 7,
+	},
+	[VCAP_AF_CLS_VID_SEL] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 37,
+		.width = 3,
+	},
+	[VCAP_AF_VID_VAL] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 43,
+		.width = 13,
+	},
+	[VCAP_AF_ISDX_ADD_REPLACE_SEL] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 66,
+		.width = 1,
+	},
+	[VCAP_AF_ISDX_VAL] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 67,
+		.width = 10,
+	},
+	[VCAP_AF_PAG_OVERRIDE_MASK] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 107,
+		.width = 8,
+	},
+	[VCAP_AF_PAG_VAL] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 115,
+		.width = 8,
+	},
+	[VCAP_AF_NXT_IDX_CTRL] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 167,
+		.width = 3,
+	},
+	[VCAP_AF_NXT_IDX] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 170,
+		.width = 10,
+	},
+};
+
+static const struct vcap_field is0_full_actionfield[] = {
+	[VCAP_AF_DSCP_ENA] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 0,
+		.width = 1,
+	},
+	[VCAP_AF_DSCP_VAL] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 1,
+		.width = 6,
+	},
+	[VCAP_AF_QOS_ENA] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 11,
+		.width = 1,
+	},
+	[VCAP_AF_QOS_VAL] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 12,
+		.width = 3,
+	},
+	[VCAP_AF_DP_ENA] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 15,
+		.width = 1,
+	},
+	[VCAP_AF_DP_VAL] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 16,
+		.width = 2,
+	},
+	[VCAP_AF_DEI_ENA] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 18,
+		.width = 1,
+	},
+	[VCAP_AF_DEI_VAL] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 19,
+		.width = 1,
+	},
+	[VCAP_AF_PCP_ENA] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 20,
+		.width = 1,
+	},
+	[VCAP_AF_PCP_VAL] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 21,
+		.width = 3,
+	},
+	[VCAP_AF_MAP_LOOKUP_SEL] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 24,
+		.width = 2,
+	},
+	[VCAP_AF_MAP_KEY] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 26,
+		.width = 3,
+	},
+	[VCAP_AF_MAP_IDX] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 29,
+		.width = 7,
+	},
+	[VCAP_AF_CLS_VID_SEL] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 36,
+		.width = 3,
+	},
+	[VCAP_AF_VID_VAL] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 42,
+		.width = 13,
+	},
+	[VCAP_AF_ISDX_ADD_REPLACE_SEL] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 65,
+		.width = 1,
+	},
+	[VCAP_AF_ISDX_VAL] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 66,
+		.width = 10,
+	},
+	[VCAP_AF_MASK_MODE] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 76,
+		.width = 3,
+	},
+	[VCAP_AF_PORT_MASK] = {
+		.type = VCAP_FIELD_U48,
+		.offset = 79,
+		.width = 37,
+	},
+	[VCAP_AF_PAG_OVERRIDE_MASK] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 174,
+		.width = 8,
+	},
+	[VCAP_AF_PAG_VAL] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 182,
+		.width = 8,
+	},
+	[VCAP_AF_NXT_IDX_CTRL] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 266,
+		.width = 3,
+	},
+	[VCAP_AF_NXT_IDX] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 269,
+		.width = 10,
+	},
+};
+
+static const struct vcap_field is0_class_reduced_actionfield[] = {
+	[VCAP_AF_TYPE] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 0,
+		.width = 1,
+	},
+	[VCAP_AF_QOS_ENA] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 5,
+		.width = 1,
+	},
+	[VCAP_AF_QOS_VAL] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 6,
+		.width = 3,
+	},
+	[VCAP_AF_DP_ENA] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 9,
+		.width = 1,
+	},
+	[VCAP_AF_DP_VAL] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 10,
+		.width = 2,
+	},
+	[VCAP_AF_MAP_LOOKUP_SEL] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 12,
+		.width = 2,
+	},
+	[VCAP_AF_MAP_KEY] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 14,
+		.width = 3,
+	},
+	[VCAP_AF_CLS_VID_SEL] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 17,
+		.width = 3,
+	},
+	[VCAP_AF_VID_VAL] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 23,
+		.width = 13,
+	},
+	[VCAP_AF_ISDX_ADD_REPLACE_SEL] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 46,
+		.width = 1,
+	},
+	[VCAP_AF_ISDX_VAL] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 47,
+		.width = 10,
+	},
+	[VCAP_AF_NXT_IDX_CTRL] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 89,
+		.width = 3,
+	},
+	[VCAP_AF_NXT_IDX] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 92,
+		.width = 10,
+	},
+};
+
+static const struct vcap_field is2_base_type_actionfield[] = {
+	[VCAP_AF_PIPELINE_FORCE_ENA] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 1,
+		.width = 1,
+	},
+	[VCAP_AF_PIPELINE_PT] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 2,
+		.width = 5,
+	},
+	[VCAP_AF_HIT_ME_ONCE] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 7,
+		.width = 1,
+	},
+	[VCAP_AF_INTR_ENA] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 8,
+		.width = 1,
+	},
+	[VCAP_AF_CPU_COPY_ENA] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 9,
+		.width = 1,
+	},
+	[VCAP_AF_CPU_QUEUE_NUM] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 10,
+		.width = 3,
+	},
+	[VCAP_AF_LRN_DIS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 15,
+		.width = 1,
+	},
+	[VCAP_AF_RT_DIS] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 16,
+		.width = 1,
+	},
+	[VCAP_AF_POLICE_ENA] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 17,
+		.width = 1,
+	},
+	[VCAP_AF_POLICE_IDX] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 18,
+		.width = 5,
+	},
+	[VCAP_AF_IGNORE_PIPELINE_CTRL] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 23,
+		.width = 1,
+	},
+	[VCAP_AF_MASK_MODE] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 27,
+		.width = 3,
+	},
+	[VCAP_AF_PORT_MASK] = {
+		.type = VCAP_FIELD_U48,
+		.offset = 30,
+		.width = 37,
+	},
+	[VCAP_AF_MIRROR_PROBE] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 78,
+		.width = 2,
+	},
+	[VCAP_AF_MATCH_ID] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 131,
+		.width = 16,
+	},
+	[VCAP_AF_MATCH_ID_MASK] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 147,
+		.width = 16,
+	},
+	[VCAP_AF_CNT_ID] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 163,
+		.width = 10,
+	},
+};
+
+static const struct vcap_field es0_es0_actionfield[] = {
+	[VCAP_AF_PUSH_OUTER_TAG] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 0,
+		.width = 2,
+	},
+	[VCAP_AF_PUSH_INNER_TAG] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 2,
+		.width = 1,
+	},
+	[VCAP_AF_TAG_A_TPID_SEL] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 3,
+		.width = 3,
+	},
+	[VCAP_AF_TAG_A_VID_SEL] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 6,
+		.width = 2,
+	},
+	[VCAP_AF_TAG_A_PCP_SEL] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 8,
+		.width = 3,
+	},
+	[VCAP_AF_TAG_A_DEI_SEL] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 11,
+		.width = 3,
+	},
+	[VCAP_AF_TAG_B_TPID_SEL] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 14,
+		.width = 3,
+	},
+	[VCAP_AF_TAG_B_VID_SEL] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 17,
+		.width = 2,
+	},
+	[VCAP_AF_TAG_B_PCP_SEL] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 19,
+		.width = 3,
+	},
+	[VCAP_AF_TAG_B_DEI_SEL] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 22,
+		.width = 3,
+	},
+	[VCAP_AF_TAG_C_TPID_SEL] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 25,
+		.width = 3,
+	},
+	[VCAP_AF_TAG_C_PCP_SEL] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 28,
+		.width = 3,
+	},
+	[VCAP_AF_TAG_C_DEI_SEL] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 31,
+		.width = 3,
+	},
+	[VCAP_AF_VID_A_VAL] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 34,
+		.width = 12,
+	},
+	[VCAP_AF_PCP_A_VAL] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 46,
+		.width = 3,
+	},
+	[VCAP_AF_DEI_A_VAL] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 49,
+		.width = 1,
+	},
+	[VCAP_AF_VID_B_VAL] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 50,
+		.width = 12,
+	},
+	[VCAP_AF_PCP_B_VAL] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 62,
+		.width = 3,
+	},
+	[VCAP_AF_DEI_B_VAL] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 65,
+		.width = 1,
+	},
+	[VCAP_AF_VID_C_VAL] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 66,
+		.width = 12,
+	},
+	[VCAP_AF_PCP_C_VAL] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 78,
+		.width = 3,
+	},
+	[VCAP_AF_DEI_C_VAL] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 81,
+		.width = 1,
+	},
+	[VCAP_AF_POP_VAL] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 82,
+		.width = 2,
+	},
+	[VCAP_AF_UNTAG_VID_ENA] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 84,
+		.width = 1,
+	},
+	[VCAP_AF_PUSH_CUSTOMER_TAG] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 85,
+		.width = 2,
+	},
+	[VCAP_AF_TAG_C_VID_SEL] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 87,
+		.width = 2,
+	},
+	[VCAP_AF_DSCP_SEL] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 127,
+		.width = 3,
+	},
+	[VCAP_AF_DSCP_VAL] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 130,
+		.width = 6,
+	},
+	[VCAP_AF_ESDX] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 319,
+		.width = 10,
+	},
+	[VCAP_AF_FWD_SEL] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 438,
+		.width = 2,
+	},
+	[VCAP_AF_CPU_QU] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 440,
+		.width = 3,
+	},
+	[VCAP_AF_PIPELINE_PT] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 443,
+		.width = 2,
+	},
+	[VCAP_AF_PIPELINE_ACT] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 445,
+		.width = 1,
+	},
+	[VCAP_AF_SWAP_MACS_ENA] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 454,
+		.width = 1,
+	},
+	[VCAP_AF_LOOP_ENA] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 455,
+		.width = 1,
+	},
+};
+
+static const struct vcap_field es2_base_type_actionfield[] = {
+	[VCAP_AF_HIT_ME_ONCE] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 0,
+		.width = 1,
+	},
+	[VCAP_AF_INTR_ENA] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 1,
+		.width = 1,
+	},
+	[VCAP_AF_FWD_MODE] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 2,
+		.width = 2,
+	},
+	[VCAP_AF_COPY_QUEUE_NUM] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 4,
+		.width = 14,
+	},
+	[VCAP_AF_COPY_PORT_NUM] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 18,
+		.width = 6,
+	},
+	[VCAP_AF_MIRROR_PROBE_ID] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 24,
+		.width = 2,
+	},
+	[VCAP_AF_CPU_COPY_ENA] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 26,
+		.width = 1,
+	},
+	[VCAP_AF_CPU_QUEUE_NUM] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 27,
+		.width = 3,
+	},
+	[VCAP_AF_POLICE_ENA] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 30,
+		.width = 1,
+	},
+	[VCAP_AF_POLICE_REMARK] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 31,
+		.width = 1,
+	},
+	[VCAP_AF_POLICE_IDX] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 32,
+		.width = 5,
+	},
+	[VCAP_AF_ES2_REW_CMD] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 37,
+		.width = 3,
+	},
+	[VCAP_AF_CNT_ID] = {
+		.type = VCAP_FIELD_U32,
+		.offset = 40,
+		.width = 9,
+	},
+	[VCAP_AF_IGNORE_PIPELINE_CTRL] = {
+		.type = VCAP_FIELD_BIT,
+		.offset = 49,
+		.width = 1,
+	},
+};
+
+/* actionfield_set */
+static const struct vcap_set is0_actionfield_set[] = {
+	[VCAP_AFS_CLASSIFICATION] = {
+		.type_id = 1,
+		.sw_per_item = 2,
+		.sw_cnt = 6,
+	},
+	[VCAP_AFS_FULL] = {
+		.type_id = -1,
+		.sw_per_item = 3,
+		.sw_cnt = 4,
+	},
+	[VCAP_AFS_CLASS_REDUCED] = {
+		.type_id = 1,
+		.sw_per_item = 1,
+		.sw_cnt = 12,
+	},
+};
+
+static const struct vcap_set is2_actionfield_set[] = {
+	[VCAP_AFS_BASE_TYPE] = {
+		.type_id = -1,
+		.sw_per_item = 3,
+		.sw_cnt = 4,
+	},
+};
+
+static const struct vcap_set es0_actionfield_set[] = {
+	[VCAP_AFS_ES0] = {
+		.type_id = -1,
+		.sw_per_item = 1,
+		.sw_cnt = 1,
+	},
+};
+
+static const struct vcap_set es2_actionfield_set[] = {
+	[VCAP_AFS_BASE_TYPE] = {
+		.type_id = -1,
+		.sw_per_item = 3,
+		.sw_cnt = 4,
+	},
+};
+
+/* actionfield_set map */
+static const struct vcap_field *is0_actionfield_set_map[] = {
+	[VCAP_AFS_CLASSIFICATION] = is0_classification_actionfield,
+	[VCAP_AFS_FULL] = is0_full_actionfield,
+	[VCAP_AFS_CLASS_REDUCED] = is0_class_reduced_actionfield,
+};
+
+static const struct vcap_field *is2_actionfield_set_map[] = {
+	[VCAP_AFS_BASE_TYPE] = is2_base_type_actionfield,
+};
+
+static const struct vcap_field *es0_actionfield_set_map[] = {
+	[VCAP_AFS_ES0] = es0_es0_actionfield,
+};
+
+static const struct vcap_field *es2_actionfield_set_map[] = {
+	[VCAP_AFS_BASE_TYPE] = es2_base_type_actionfield,
+};
+
+/* actionfield_set map size */
+static int is0_actionfield_set_map_size[] = {
+	[VCAP_AFS_CLASSIFICATION] = ARRAY_SIZE(is0_classification_actionfield),
+	[VCAP_AFS_FULL] = ARRAY_SIZE(is0_full_actionfield),
+	[VCAP_AFS_CLASS_REDUCED] = ARRAY_SIZE(is0_class_reduced_actionfield),
+};
+
+static int is2_actionfield_set_map_size[] = {
+	[VCAP_AFS_BASE_TYPE] = ARRAY_SIZE(is2_base_type_actionfield),
+};
+
+static int es0_actionfield_set_map_size[] = {
+	[VCAP_AFS_ES0] = ARRAY_SIZE(es0_es0_actionfield),
+};
+
+static int es2_actionfield_set_map_size[] = {
+	[VCAP_AFS_BASE_TYPE] = ARRAY_SIZE(es2_base_type_actionfield),
+};
+
+/* Type Groups */
+static const struct vcap_typegroup is0_x12_keyfield_set_typegroups[] = {
+	{
+		.offset = 0,
+		.width = 5,
+		.value = 16,
+	},
+	{
+		.offset = 52,
+		.width = 1,
+		.value = 0,
+	},
+	{
+		.offset = 104,
+		.width = 2,
+		.value = 0,
+	},
+	{
+		.offset = 156,
+		.width = 3,
+		.value = 0,
+	},
+	{
+		.offset = 208,
+		.width = 2,
+		.value = 0,
+	},
+	{
+		.offset = 260,
+		.width = 1,
+		.value = 0,
+	},
+	{
+		.offset = 312,
+		.width = 4,
+		.value = 0,
+	},
+	{
+		.offset = 364,
+		.width = 1,
+		.value = 0,
+	},
+	{
+		.offset = 416,
+		.width = 2,
+		.value = 0,
+	},
+	{
+		.offset = 468,
+		.width = 3,
+		.value = 0,
+	},
+	{
+		.offset = 520,
+		.width = 2,
+		.value = 0,
+	},
+	{
+		.offset = 572,
+		.width = 1,
+		.value = 0,
+	},
+	{}
+};
+
+static const struct vcap_typegroup is0_x6_keyfield_set_typegroups[] = {
+	{
+		.offset = 0,
+		.width = 4,
+		.value = 8,
+	},
+	{
+		.offset = 52,
+		.width = 1,
+		.value = 0,
+	},
+	{
+		.offset = 104,
+		.width = 2,
+		.value = 0,
+	},
+	{
+		.offset = 156,
+		.width = 3,
+		.value = 0,
+	},
+	{
+		.offset = 208,
+		.width = 2,
+		.value = 0,
+	},
+	{
+		.offset = 260,
+		.width = 1,
+		.value = 0,
+	},
+	{}
+};
+
+static const struct vcap_typegroup is0_x3_keyfield_set_typegroups[] = {
+	{}
+};
+
+static const struct vcap_typegroup is0_x2_keyfield_set_typegroups[] = {
+	{}
+};
+
+static const struct vcap_typegroup is0_x1_keyfield_set_typegroups[] = {
+	{}
+};
+
+static const struct vcap_typegroup is2_x12_keyfield_set_typegroups[] = {
+	{
+		.offset = 0,
+		.width = 3,
+		.value = 4,
+	},
+	{
+		.offset = 156,
+		.width = 1,
+		.value = 0,
+	},
+	{
+		.offset = 312,
+		.width = 2,
+		.value = 0,
+	},
+	{
+		.offset = 468,
+		.width = 1,
+		.value = 0,
+	},
+	{}
+};
+
+static const struct vcap_typegroup is2_x6_keyfield_set_typegroups[] = {
+	{
+		.offset = 0,
+		.width = 2,
+		.value = 2,
+	},
+	{
+		.offset = 156,
+		.width = 1,
+		.value = 0,
+	},
+	{}
+};
+
+static const struct vcap_typegroup is2_x3_keyfield_set_typegroups[] = {
+	{}
+};
+
+static const struct vcap_typegroup is2_x1_keyfield_set_typegroups[] = {
+	{}
+};
+
+static const struct vcap_typegroup es0_x1_keyfield_set_typegroups[] = {
+	{}
+};
+
+static const struct vcap_typegroup es2_x12_keyfield_set_typegroups[] = {
+	{
+		.offset = 0,
+		.width = 3,
+		.value = 4,
+	},
+	{
+		.offset = 156,
+		.width = 1,
+		.value = 0,
+	},
+	{
+		.offset = 312,
+		.width = 2,
+		.value = 0,
+	},
+	{
+		.offset = 468,
+		.width = 1,
+		.value = 0,
+	},
+	{}
+};
+
+static const struct vcap_typegroup es2_x6_keyfield_set_typegroups[] = {
+	{
+		.offset = 0,
+		.width = 2,
+		.value = 2,
+	},
+	{
+		.offset = 156,
+		.width = 1,
+		.value = 0,
+	},
+	{}
+};
+
+static const struct vcap_typegroup es2_x3_keyfield_set_typegroups[] = {
+	{}
+};
+
+static const struct vcap_typegroup es2_x1_keyfield_set_typegroups[] = {
+	{}
+};
+
+static const struct vcap_typegroup *is0_keyfield_set_typegroups[] = {
+	[12] = is0_x12_keyfield_set_typegroups,
+	[6] = is0_x6_keyfield_set_typegroups,
+	[3] = is0_x3_keyfield_set_typegroups,
+	[2] = is0_x2_keyfield_set_typegroups,
+	[1] = is0_x1_keyfield_set_typegroups,
+	[13] = NULL,
+};
+
+static const struct vcap_typegroup *is2_keyfield_set_typegroups[] = {
+	[12] = is2_x12_keyfield_set_typegroups,
+	[6] = is2_x6_keyfield_set_typegroups,
+	[3] = is2_x3_keyfield_set_typegroups,
+	[1] = is2_x1_keyfield_set_typegroups,
+	[13] = NULL,
+};
+
+static const struct vcap_typegroup *es0_keyfield_set_typegroups[] = {
+	[1] = es0_x1_keyfield_set_typegroups,
+	[2] = NULL,
+};
+
+static const struct vcap_typegroup *es2_keyfield_set_typegroups[] = {
+	[12] = es2_x12_keyfield_set_typegroups,
+	[6] = es2_x6_keyfield_set_typegroups,
+	[3] = es2_x3_keyfield_set_typegroups,
+	[1] = es2_x1_keyfield_set_typegroups,
+	[13] = NULL,
+};
+
+static const struct vcap_typegroup is0_x3_actionfield_set_typegroups[] = {
+	{
+		.offset = 0,
+		.width = 3,
+		.value = 4,
+	},
+	{
+		.offset = 103,
+		.width = 2,
+		.value = 0,
+	},
+	{
+		.offset = 206,
+		.width = 2,
+		.value = 0,
+	},
+	{}
+};
+
+static const struct vcap_typegroup is0_x2_actionfield_set_typegroups[] = {
+	{
+		.offset = 0,
+		.width = 2,
+		.value = 2,
+	},
+	{
+		.offset = 103,
+		.width = 1,
+		.value = 0,
+	},
+	{}
+};
+
+static const struct vcap_typegroup is0_x1_actionfield_set_typegroups[] = {
+	{
+		.offset = 0,
+		.width = 1,
+		.value = 1,
+	},
+	{}
+};
+
+static const struct vcap_typegroup is2_x3_actionfield_set_typegroups[] = {
+	{
+		.offset = 0,
+		.width = 2,
+		.value = 2,
+	},
+	{
+		.offset = 95,
+		.width = 1,
+		.value = 0,
+	},
+	{
+		.offset = 190,
+		.width = 1,
+		.value = 0,
+	},
+	{}
+};
+
+static const struct vcap_typegroup is2_x1_actionfield_set_typegroups[] = {
+	{}
+};
+
+static const struct vcap_typegroup es0_x1_actionfield_set_typegroups[] = {
+	{}
+};
+
+static const struct vcap_typegroup es2_x3_actionfield_set_typegroups[] = {
+	{
+		.offset = 0,
+		.width = 2,
+		.value = 2,
+	},
+	{
+		.offset = 19,
+		.width = 1,
+		.value = 0,
+	},
+	{
+		.offset = 38,
+		.width = 1,
+		.value = 0,
+	},
+	{}
+};
+
+static const struct vcap_typegroup es2_x1_actionfield_set_typegroups[] = {
+	{}
+};
+
+static const struct vcap_typegroup *is0_actionfield_set_typegroups[] = {
+	[3] = is0_x3_actionfield_set_typegroups,
+	[2] = is0_x2_actionfield_set_typegroups,
+	[1] = is0_x1_actionfield_set_typegroups,
+	[13] = NULL,
+};
+
+static const struct vcap_typegroup *is2_actionfield_set_typegroups[] = {
+	[3] = is2_x3_actionfield_set_typegroups,
+	[1] = is2_x1_actionfield_set_typegroups,
+	[13] = NULL,
+};
+
+static const struct vcap_typegroup *es0_actionfield_set_typegroups[] = {
+	[1] = es0_x1_actionfield_set_typegroups,
+	[2] = NULL,
+};
+
+static const struct vcap_typegroup *es2_actionfield_set_typegroups[] = {
+	[3] = es2_x3_actionfield_set_typegroups,
+	[1] = es2_x1_actionfield_set_typegroups,
+	[13] = NULL,
+};
+
+/* Keyfieldset names */
+static const char * const vcap_keyfield_set_names[] = {
+	[VCAP_KFS_NO_VALUE]                      =  "(None)",
+	[VCAP_KFS_ARP]                           =  "VCAP_KFS_ARP",
+	[VCAP_KFS_ETAG]                          =  "VCAP_KFS_ETAG",
+	[VCAP_KFS_IP4_OTHER]                     =  "VCAP_KFS_IP4_OTHER",
+	[VCAP_KFS_IP4_TCP_UDP]                   =  "VCAP_KFS_IP4_TCP_UDP",
+	[VCAP_KFS_IP4_VID]                       =  "VCAP_KFS_IP4_VID",
+	[VCAP_KFS_IP6_OTHER]                     =  "VCAP_KFS_IP6_OTHER",
+	[VCAP_KFS_IP6_STD]                       =  "VCAP_KFS_IP6_STD",
+	[VCAP_KFS_IP6_TCP_UDP]                   =  "VCAP_KFS_IP6_TCP_UDP",
+	[VCAP_KFS_IP6_VID]                       =  "VCAP_KFS_IP6_VID",
+	[VCAP_KFS_IP_7TUPLE]                     =  "VCAP_KFS_IP_7TUPLE",
+	[VCAP_KFS_ISDX]                          =  "VCAP_KFS_ISDX",
+	[VCAP_KFS_LL_FULL]                       =  "VCAP_KFS_LL_FULL",
+	[VCAP_KFS_MAC_ETYPE]                     =  "VCAP_KFS_MAC_ETYPE",
+	[VCAP_KFS_MAC_LLC]                       =  "VCAP_KFS_MAC_LLC",
+	[VCAP_KFS_MAC_SNAP]                      =  "VCAP_KFS_MAC_SNAP",
+	[VCAP_KFS_NORMAL_5TUPLE_IP4]             =  "VCAP_KFS_NORMAL_5TUPLE_IP4",
+	[VCAP_KFS_NORMAL_7TUPLE]                 =  "VCAP_KFS_NORMAL_7TUPLE",
+	[VCAP_KFS_OAM]                           =  "VCAP_KFS_OAM",
+	[VCAP_KFS_PURE_5TUPLE_IP4]               =  "VCAP_KFS_PURE_5TUPLE_IP4",
+	[VCAP_KFS_SMAC_SIP4]                     =  "VCAP_KFS_SMAC_SIP4",
+	[VCAP_KFS_SMAC_SIP6]                     =  "VCAP_KFS_SMAC_SIP6",
+};
+
+/* Actionfieldset names */
+static const char * const vcap_actionfield_set_names[] = {
+	[VCAP_AFS_NO_VALUE]                      =  "(None)",
+	[VCAP_AFS_BASE_TYPE]                     =  "VCAP_AFS_BASE_TYPE",
+	[VCAP_AFS_CLASSIFICATION]                =  "VCAP_AFS_CLASSIFICATION",
+	[VCAP_AFS_CLASS_REDUCED]                 =  "VCAP_AFS_CLASS_REDUCED",
+	[VCAP_AFS_ES0]                           =  "VCAP_AFS_ES0",
+	[VCAP_AFS_FULL]                          =  "VCAP_AFS_FULL",
+	[VCAP_AFS_SMAC_SIP]                      =  "VCAP_AFS_SMAC_SIP",
+};
+
+/* Keyfield names */
+static const char * const vcap_keyfield_names[] = {
+	[VCAP_KF_NO_VALUE]                       =  "(None)",
+	[VCAP_KF_8021BR_ECID_BASE]               =  "8021BR_ECID_BASE",
+	[VCAP_KF_8021BR_ECID_EXT]                =  "8021BR_ECID_EXT",
+	[VCAP_KF_8021BR_E_TAGGED]                =  "8021BR_E_TAGGED",
+	[VCAP_KF_8021BR_GRP]                     =  "8021BR_GRP",
+	[VCAP_KF_8021BR_IGR_ECID_BASE]           =  "8021BR_IGR_ECID_BASE",
+	[VCAP_KF_8021BR_IGR_ECID_EXT]            =  "8021BR_IGR_ECID_EXT",
+	[VCAP_KF_8021Q_DEI0]                     =  "8021Q_DEI0",
+	[VCAP_KF_8021Q_DEI1]                     =  "8021Q_DEI1",
+	[VCAP_KF_8021Q_DEI2]                     =  "8021Q_DEI2",
+	[VCAP_KF_8021Q_DEI_CLS]                  =  "8021Q_DEI_CLS",
+	[VCAP_KF_8021Q_PCP0]                     =  "8021Q_PCP0",
+	[VCAP_KF_8021Q_PCP1]                     =  "8021Q_PCP1",
+	[VCAP_KF_8021Q_PCP2]                     =  "8021Q_PCP2",
+	[VCAP_KF_8021Q_PCP_CLS]                  =  "8021Q_PCP_CLS",
+	[VCAP_KF_8021Q_TPID]                     =  "8021Q_TPID",
+	[VCAP_KF_8021Q_TPID0]                    =  "8021Q_TPID0",
+	[VCAP_KF_8021Q_TPID1]                    =  "8021Q_TPID1",
+	[VCAP_KF_8021Q_TPID2]                    =  "8021Q_TPID2",
+	[VCAP_KF_8021Q_VID0]                     =  "8021Q_VID0",
+	[VCAP_KF_8021Q_VID1]                     =  "8021Q_VID1",
+	[VCAP_KF_8021Q_VID2]                     =  "8021Q_VID2",
+	[VCAP_KF_8021Q_VID_CLS]                  =  "8021Q_VID_CLS",
+	[VCAP_KF_8021Q_VLAN_TAGGED_IS]           =  "8021Q_VLAN_TAGGED_IS",
+	[VCAP_KF_8021Q_VLAN_TAGS]                =  "8021Q_VLAN_TAGS",
+	[VCAP_KF_ACL_GRP_ID]                     =  "ACL_GRP_ID",
+	[VCAP_KF_ARP_ADDR_SPACE_OK_IS]           =  "ARP_ADDR_SPACE_OK_IS",
+	[VCAP_KF_ARP_LEN_OK_IS]                  =  "ARP_LEN_OK_IS",
+	[VCAP_KF_ARP_OPCODE]                     =  "ARP_OPCODE",
+	[VCAP_KF_ARP_OPCODE_UNKNOWN_IS]          =  "ARP_OPCODE_UNKNOWN_IS",
+	[VCAP_KF_ARP_PROTO_SPACE_OK_IS]          =  "ARP_PROTO_SPACE_OK_IS",
+	[VCAP_KF_ARP_SENDER_MATCH_IS]            =  "ARP_SENDER_MATCH_IS",
+	[VCAP_KF_ARP_TGT_MATCH_IS]               =  "ARP_TGT_MATCH_IS",
+	[VCAP_KF_COSID_CLS]                      =  "COSID_CLS",
+	[VCAP_KF_ES0_ISDX_KEY_ENA]               =  "ES0_ISDX_KEY_ENA",
+	[VCAP_KF_ETYPE]                          =  "ETYPE",
+	[VCAP_KF_ETYPE_LEN_IS]                   =  "ETYPE_LEN_IS",
+	[VCAP_KF_HOST_MATCH]                     =  "HOST_MATCH",
+	[VCAP_KF_IF_EGR_PORT_MASK]               =  "IF_EGR_PORT_MASK",
+	[VCAP_KF_IF_EGR_PORT_MASK_RNG]           =  "IF_EGR_PORT_MASK_RNG",
+	[VCAP_KF_IF_EGR_PORT_NO]                 =  "IF_EGR_PORT_NO",
+	[VCAP_KF_IF_IGR_PORT]                    =  "IF_IGR_PORT",
+	[VCAP_KF_IF_IGR_PORT_MASK]               =  "IF_IGR_PORT_MASK",
+	[VCAP_KF_IF_IGR_PORT_MASK_L3]            =  "IF_IGR_PORT_MASK_L3",
+	[VCAP_KF_IF_IGR_PORT_MASK_RNG]           =  "IF_IGR_PORT_MASK_RNG",
+	[VCAP_KF_IF_IGR_PORT_MASK_SEL]           =  "IF_IGR_PORT_MASK_SEL",
+	[VCAP_KF_IF_IGR_PORT_SEL]                =  "IF_IGR_PORT_SEL",
+	[VCAP_KF_IP4_IS]                         =  "IP4_IS",
+	[VCAP_KF_IP_MC_IS]                       =  "IP_MC_IS",
+	[VCAP_KF_IP_PAYLOAD_5TUPLE]              =  "IP_PAYLOAD_5TUPLE",
+	[VCAP_KF_IP_SNAP_IS]                     =  "IP_SNAP_IS",
+	[VCAP_KF_ISDX_CLS]                       =  "ISDX_CLS",
+	[VCAP_KF_ISDX_GT0_IS]                    =  "ISDX_GT0_IS",
+	[VCAP_KF_L2_BC_IS]                       =  "L2_BC_IS",
+	[VCAP_KF_L2_DMAC]                        =  "L2_DMAC",
+	[VCAP_KF_L2_FRM_TYPE]                    =  "L2_FRM_TYPE",
+	[VCAP_KF_L2_FWD_IS]                      =  "L2_FWD_IS",
+	[VCAP_KF_L2_LLC]                         =  "L2_LLC",
+	[VCAP_KF_L2_MC_IS]                       =  "L2_MC_IS",
+	[VCAP_KF_L2_PAYLOAD0]                    =  "L2_PAYLOAD0",
+	[VCAP_KF_L2_PAYLOAD1]                    =  "L2_PAYLOAD1",
+	[VCAP_KF_L2_PAYLOAD2]                    =  "L2_PAYLOAD2",
+	[VCAP_KF_L2_PAYLOAD_ETYPE]               =  "L2_PAYLOAD_ETYPE",
+	[VCAP_KF_L2_SMAC]                        =  "L2_SMAC",
+	[VCAP_KF_L2_SNAP]                        =  "L2_SNAP",
+	[VCAP_KF_L3_DIP_EQ_SIP_IS]               =  "L3_DIP_EQ_SIP_IS",
+	[VCAP_KF_L3_DPL_CLS]                     =  "L3_DPL_CLS",
+	[VCAP_KF_L3_DSCP]                        =  "L3_DSCP",
+	[VCAP_KF_L3_DST_IS]                      =  "L3_DST_IS",
+	[VCAP_KF_L3_FRAGMENT]                    =  "L3_FRAGMENT",
+	[VCAP_KF_L3_FRAGMENT_TYPE]               =  "L3_FRAGMENT_TYPE",
+	[VCAP_KF_L3_FRAG_INVLD_L4_LEN]           =  "L3_FRAG_INVLD_L4_LEN",
+	[VCAP_KF_L3_FRAG_OFS_GT0]                =  "L3_FRAG_OFS_GT0",
+	[VCAP_KF_L3_IP4_DIP]                     =  "L3_IP4_DIP",
+	[VCAP_KF_L3_IP4_SIP]                     =  "L3_IP4_SIP",
+	[VCAP_KF_L3_IP6_DIP]                     =  "L3_IP6_DIP",
+	[VCAP_KF_L3_IP6_SIP]                     =  "L3_IP6_SIP",
+	[VCAP_KF_L3_IP_PROTO]                    =  "L3_IP_PROTO",
+	[VCAP_KF_L3_OPTIONS_IS]                  =  "L3_OPTIONS_IS",
+	[VCAP_KF_L3_PAYLOAD]                     =  "L3_PAYLOAD",
+	[VCAP_KF_L3_RT_IS]                       =  "L3_RT_IS",
+	[VCAP_KF_L3_TOS]                         =  "L3_TOS",
+	[VCAP_KF_L3_TTL_GT0]                     =  "L3_TTL_GT0",
+	[VCAP_KF_L4_1588_DOM]                    =  "L4_1588_DOM",
+	[VCAP_KF_L4_1588_VER]                    =  "L4_1588_VER",
+	[VCAP_KF_L4_ACK]                         =  "L4_ACK",
+	[VCAP_KF_L4_DPORT]                       =  "L4_DPORT",
+	[VCAP_KF_L4_FIN]                         =  "L4_FIN",
+	[VCAP_KF_L4_PAYLOAD]                     =  "L4_PAYLOAD",
+	[VCAP_KF_L4_PSH]                         =  "L4_PSH",
+	[VCAP_KF_L4_RNG]                         =  "L4_RNG",
+	[VCAP_KF_L4_RST]                         =  "L4_RST",
+	[VCAP_KF_L4_SEQUENCE_EQ0_IS]             =  "L4_SEQUENCE_EQ0_IS",
+	[VCAP_KF_L4_SPORT]                       =  "L4_SPORT",
+	[VCAP_KF_L4_SPORT_EQ_DPORT_IS]           =  "L4_SPORT_EQ_DPORT_IS",
+	[VCAP_KF_L4_SYN]                         =  "L4_SYN",
+	[VCAP_KF_L4_URG]                         =  "L4_URG",
+	[VCAP_KF_LOOKUP_FIRST_IS]                =  "LOOKUP_FIRST_IS",
+	[VCAP_KF_LOOKUP_GEN_IDX]                 =  "LOOKUP_GEN_IDX",
+	[VCAP_KF_LOOKUP_GEN_IDX_SEL]             =  "LOOKUP_GEN_IDX_SEL",
+	[VCAP_KF_LOOKUP_PAG]                     =  "LOOKUP_PAG",
+	[VCAP_KF_MIRROR_PROBE]                   =  "MIRROR_PROBE",
+	[VCAP_KF_OAM_CCM_CNTS_EQ0]               =  "OAM_CCM_CNTS_EQ0",
+	[VCAP_KF_OAM_DETECTED]                   =  "OAM_DETECTED",
+	[VCAP_KF_OAM_FLAGS]                      =  "OAM_FLAGS",
+	[VCAP_KF_OAM_MEL_FLAGS]                  =  "OAM_MEL_FLAGS",
+	[VCAP_KF_OAM_MEPID]                      =  "OAM_MEPID",
+	[VCAP_KF_OAM_OPCODE]                     =  "OAM_OPCODE",
+	[VCAP_KF_OAM_VER]                        =  "OAM_VER",
+	[VCAP_KF_OAM_Y1731_IS]                   =  "OAM_Y1731_IS",
+	[VCAP_KF_PROT_ACTIVE]                    =  "PROT_ACTIVE",
+	[VCAP_KF_TCP_IS]                         =  "TCP_IS",
+	[VCAP_KF_TCP_UDP_IS]                     =  "TCP_UDP_IS",
+	[VCAP_KF_TYPE]                           =  "TYPE",
+};
+
+/* Actionfield names */
+static const char * const vcap_actionfield_names[] = {
+	[VCAP_AF_NO_VALUE]                       =  "(None)",
+	[VCAP_AF_ACL_ID]                         =  "ACL_ID",
+	[VCAP_AF_CLS_VID_SEL]                    =  "CLS_VID_SEL",
+	[VCAP_AF_CNT_ID]                         =  "CNT_ID",
+	[VCAP_AF_COPY_PORT_NUM]                  =  "COPY_PORT_NUM",
+	[VCAP_AF_COPY_QUEUE_NUM]                 =  "COPY_QUEUE_NUM",
+	[VCAP_AF_CPU_COPY_ENA]                   =  "CPU_COPY_ENA",
+	[VCAP_AF_CPU_QU]                         =  "CPU_QU",
+	[VCAP_AF_CPU_QUEUE_NUM]                  =  "CPU_QUEUE_NUM",
+	[VCAP_AF_DEI_A_VAL]                      =  "DEI_A_VAL",
+	[VCAP_AF_DEI_B_VAL]                      =  "DEI_B_VAL",
+	[VCAP_AF_DEI_C_VAL]                      =  "DEI_C_VAL",
+	[VCAP_AF_DEI_ENA]                        =  "DEI_ENA",
+	[VCAP_AF_DEI_VAL]                        =  "DEI_VAL",
+	[VCAP_AF_DP_ENA]                         =  "DP_ENA",
+	[VCAP_AF_DP_VAL]                         =  "DP_VAL",
+	[VCAP_AF_DSCP_ENA]                       =  "DSCP_ENA",
+	[VCAP_AF_DSCP_SEL]                       =  "DSCP_SEL",
+	[VCAP_AF_DSCP_VAL]                       =  "DSCP_VAL",
+	[VCAP_AF_ES2_REW_CMD]                    =  "ES2_REW_CMD",
+	[VCAP_AF_ESDX]                           =  "ESDX",
+	[VCAP_AF_FWD_KILL_ENA]                   =  "FWD_KILL_ENA",
+	[VCAP_AF_FWD_MODE]                       =  "FWD_MODE",
+	[VCAP_AF_FWD_SEL]                        =  "FWD_SEL",
+	[VCAP_AF_HIT_ME_ONCE]                    =  "HIT_ME_ONCE",
+	[VCAP_AF_HOST_MATCH]                     =  "HOST_MATCH",
+	[VCAP_AF_IGNORE_PIPELINE_CTRL]           =  "IGNORE_PIPELINE_CTRL",
+	[VCAP_AF_INTR_ENA]                       =  "INTR_ENA",
+	[VCAP_AF_ISDX_ADD_REPLACE_SEL]           =  "ISDX_ADD_REPLACE_SEL",
+	[VCAP_AF_ISDX_ENA]                       =  "ISDX_ENA",
+	[VCAP_AF_ISDX_VAL]                       =  "ISDX_VAL",
+	[VCAP_AF_LOOP_ENA]                       =  "LOOP_ENA",
+	[VCAP_AF_LRN_DIS]                        =  "LRN_DIS",
+	[VCAP_AF_MAP_IDX]                        =  "MAP_IDX",
+	[VCAP_AF_MAP_KEY]                        =  "MAP_KEY",
+	[VCAP_AF_MAP_LOOKUP_SEL]                 =  "MAP_LOOKUP_SEL",
+	[VCAP_AF_MASK_MODE]                      =  "MASK_MODE",
+	[VCAP_AF_MATCH_ID]                       =  "MATCH_ID",
+	[VCAP_AF_MATCH_ID_MASK]                  =  "MATCH_ID_MASK",
+	[VCAP_AF_MIRROR_ENA]                     =  "MIRROR_ENA",
+	[VCAP_AF_MIRROR_PROBE]                   =  "MIRROR_PROBE",
+	[VCAP_AF_MIRROR_PROBE_ID]                =  "MIRROR_PROBE_ID",
+	[VCAP_AF_NXT_IDX]                        =  "NXT_IDX",
+	[VCAP_AF_NXT_IDX_CTRL]                   =  "NXT_IDX_CTRL",
+	[VCAP_AF_PAG_OVERRIDE_MASK]              =  "PAG_OVERRIDE_MASK",
+	[VCAP_AF_PAG_VAL]                        =  "PAG_VAL",
+	[VCAP_AF_PCP_A_VAL]                      =  "PCP_A_VAL",
+	[VCAP_AF_PCP_B_VAL]                      =  "PCP_B_VAL",
+	[VCAP_AF_PCP_C_VAL]                      =  "PCP_C_VAL",
+	[VCAP_AF_PCP_ENA]                        =  "PCP_ENA",
+	[VCAP_AF_PCP_VAL]                        =  "PCP_VAL",
+	[VCAP_AF_PIPELINE_ACT]                   =  "PIPELINE_ACT",
+	[VCAP_AF_PIPELINE_FORCE_ENA]             =  "PIPELINE_FORCE_ENA",
+	[VCAP_AF_PIPELINE_PT]                    =  "PIPELINE_PT",
+	[VCAP_AF_POLICE_ENA]                     =  "POLICE_ENA",
+	[VCAP_AF_POLICE_IDX]                     =  "POLICE_IDX",
+	[VCAP_AF_POLICE_REMARK]                  =  "POLICE_REMARK",
+	[VCAP_AF_POLICE_VCAP_ONLY]               =  "POLICE_VCAP_ONLY",
+	[VCAP_AF_POP_VAL]                        =  "POP_VAL",
+	[VCAP_AF_PORT_MASK]                      =  "PORT_MASK",
+	[VCAP_AF_PUSH_CUSTOMER_TAG]              =  "PUSH_CUSTOMER_TAG",
+	[VCAP_AF_PUSH_INNER_TAG]                 =  "PUSH_INNER_TAG",
+	[VCAP_AF_PUSH_OUTER_TAG]                 =  "PUSH_OUTER_TAG",
+	[VCAP_AF_QOS_ENA]                        =  "QOS_ENA",
+	[VCAP_AF_QOS_VAL]                        =  "QOS_VAL",
+	[VCAP_AF_REW_OP]                         =  "REW_OP",
+	[VCAP_AF_RT_DIS]                         =  "RT_DIS",
+	[VCAP_AF_SWAP_MACS_ENA]                  =  "SWAP_MACS_ENA",
+	[VCAP_AF_TAG_A_DEI_SEL]                  =  "TAG_A_DEI_SEL",
+	[VCAP_AF_TAG_A_PCP_SEL]                  =  "TAG_A_PCP_SEL",
+	[VCAP_AF_TAG_A_TPID_SEL]                 =  "TAG_A_TPID_SEL",
+	[VCAP_AF_TAG_A_VID_SEL]                  =  "TAG_A_VID_SEL",
+	[VCAP_AF_TAG_B_DEI_SEL]                  =  "TAG_B_DEI_SEL",
+	[VCAP_AF_TAG_B_PCP_SEL]                  =  "TAG_B_PCP_SEL",
+	[VCAP_AF_TAG_B_TPID_SEL]                 =  "TAG_B_TPID_SEL",
+	[VCAP_AF_TAG_B_VID_SEL]                  =  "TAG_B_VID_SEL",
+	[VCAP_AF_TAG_C_DEI_SEL]                  =  "TAG_C_DEI_SEL",
+	[VCAP_AF_TAG_C_PCP_SEL]                  =  "TAG_C_PCP_SEL",
+	[VCAP_AF_TAG_C_TPID_SEL]                 =  "TAG_C_TPID_SEL",
+	[VCAP_AF_TAG_C_VID_SEL]                  =  "TAG_C_VID_SEL",
+	[VCAP_AF_TYPE]                           =  "TYPE",
+	[VCAP_AF_UNTAG_VID_ENA]                  =  "UNTAG_VID_ENA",
+	[VCAP_AF_VID_A_VAL]                      =  "VID_A_VAL",
+	[VCAP_AF_VID_B_VAL]                      =  "VID_B_VAL",
+	[VCAP_AF_VID_C_VAL]                      =  "VID_C_VAL",
+	[VCAP_AF_VID_VAL]                        =  "VID_VAL",
+};
+
+/* VCAPs */
+const struct vcap_info lan969x_vcaps[] = {
+	[VCAP_TYPE_IS0] = {
+		.name = "is0",
+		.rows = 256,
+		.sw_count = 12,
+		.sw_width = 52,
+		.sticky_width = 1,
+		.act_width = 103,
+		.default_cnt = 70,
+		.require_cnt_dis = 0,
+		.version = 1,
+		.keyfield_set = is0_keyfield_set,
+		.keyfield_set_size = ARRAY_SIZE(is0_keyfield_set),
+		.actionfield_set = is0_actionfield_set,
+		.actionfield_set_size = ARRAY_SIZE(is0_actionfield_set),
+		.keyfield_set_map = is0_keyfield_set_map,
+		.keyfield_set_map_size = is0_keyfield_set_map_size,
+		.actionfield_set_map = is0_actionfield_set_map,
+		.actionfield_set_map_size = is0_actionfield_set_map_size,
+		.keyfield_set_typegroups = is0_keyfield_set_typegroups,
+		.actionfield_set_typegroups = is0_actionfield_set_typegroups,
+	},
+	[VCAP_TYPE_IS2] = {
+		.name = "is2",
+		.rows = 256,
+		.sw_count = 12,
+		.sw_width = 52,
+		.sticky_width = 1,
+		.act_width = 103,
+		.default_cnt = 38,
+		.require_cnt_dis = 0,
+		.version = 1,
+		.keyfield_set = is2_keyfield_set,
+		.keyfield_set_size = ARRAY_SIZE(is2_keyfield_set),
+		.actionfield_set = is2_actionfield_set,
+		.actionfield_set_size = ARRAY_SIZE(is2_actionfield_set),
+		.keyfield_set_map = is2_keyfield_set_map,
+		.keyfield_set_map_size = is2_keyfield_set_map_size,
+		.actionfield_set_map = is2_actionfield_set_map,
+		.actionfield_set_map_size = is2_actionfield_set_map_size,
+		.keyfield_set_typegroups = is2_keyfield_set_typegroups,
+		.actionfield_set_typegroups = is2_actionfield_set_typegroups,
+	},
+	[VCAP_TYPE_ES0] = {
+		.name = "es0",
+		.rows = 1536,
+		.sw_count = 1,
+		.sw_width = 51,
+		.sticky_width = 1,
+		.act_width = 469,
+		.default_cnt = 35,
+		.require_cnt_dis = 0,
+		.version = 1,
+		.keyfield_set = es0_keyfield_set,
+		.keyfield_set_size = ARRAY_SIZE(es0_keyfield_set),
+		.actionfield_set = es0_actionfield_set,
+		.actionfield_set_size = ARRAY_SIZE(es0_actionfield_set),
+		.keyfield_set_map = es0_keyfield_set_map,
+		.keyfield_set_map_size = es0_keyfield_set_map_size,
+		.actionfield_set_map = es0_actionfield_set_map,
+		.actionfield_set_map_size = es0_actionfield_set_map_size,
+		.keyfield_set_typegroups = es0_keyfield_set_typegroups,
+		.actionfield_set_typegroups = es0_actionfield_set_typegroups,
+	},
+	[VCAP_TYPE_ES2] = {
+		.name = "es2",
+		.rows = 256,
+		.sw_count = 12,
+		.sw_width = 52,
+		.sticky_width = 1,
+		.act_width = 19,
+		.default_cnt = 39,
+		.require_cnt_dis = 0,
+		.version = 1,
+		.keyfield_set = es2_keyfield_set,
+		.keyfield_set_size = ARRAY_SIZE(es2_keyfield_set),
+		.actionfield_set = es2_actionfield_set,
+		.actionfield_set_size = ARRAY_SIZE(es2_actionfield_set),
+		.keyfield_set_map = es2_keyfield_set_map,
+		.keyfield_set_map_size = es2_keyfield_set_map_size,
+		.actionfield_set_map = es2_actionfield_set_map,
+		.actionfield_set_map_size = es2_actionfield_set_map_size,
+		.keyfield_set_typegroups = es2_keyfield_set_typegroups,
+		.actionfield_set_typegroups = es2_actionfield_set_typegroups,
+	},
+};
+
+const struct vcap_statistics lan969x_vcap_stats = {
+	.name = "lan969x",
+	.count = 4,
+	.keyfield_set_names = vcap_keyfield_set_names,
+	.actionfield_set_names = vcap_actionfield_set_names,
+	.keyfield_names = vcap_keyfield_names,
+	.actionfield_names = vcap_actionfield_names,
+};
--- /dev/null
+++ b/drivers/net/ethernet/microchip/sparx5/lan969x/lan969x_vcap_impl.c
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: GPL-2.0+
+
+#include "vcap_api.h"
+#include "lan969x.h"
+
+const struct sparx5_vcap_inst lan969x_vcap_inst_cfg[] = {
+	{
+		.vtype = VCAP_TYPE_IS0, /* CLM-0 */
+		.vinst = 0,
+		.map_id = 1,
+		.lookups = SPARX5_IS0_LOOKUPS,
+		.lookups_per_instance = SPARX5_IS0_LOOKUPS / 3,
+		.first_cid = SPARX5_VCAP_CID_IS0_L0,
+		.last_cid = SPARX5_VCAP_CID_IS0_L2 - 1,
+		.blockno = 2,
+		.blocks = 1,
+		.ingress = true,
+	},
+	{
+		.vtype = VCAP_TYPE_IS0, /* CLM-1 */
+		.vinst = 1,
+		.map_id = 2,
+		.lookups = SPARX5_IS0_LOOKUPS,
+		.lookups_per_instance = SPARX5_IS0_LOOKUPS / 3,
+		.first_cid = SPARX5_VCAP_CID_IS0_L2,
+		.last_cid = SPARX5_VCAP_CID_IS0_L4 - 1,
+		.blockno = 3,
+		.blocks = 1,
+		.ingress = true,
+	},
+	{
+		.vtype = VCAP_TYPE_IS0, /* CLM-2 */
+		.vinst = 2,
+		.map_id = 3,
+		.lookups = SPARX5_IS0_LOOKUPS,
+		.lookups_per_instance = SPARX5_IS0_LOOKUPS / 3,
+		.first_cid = SPARX5_VCAP_CID_IS0_L4,
+		.last_cid = SPARX5_VCAP_CID_IS0_MAX,
+		.blockno = 4,
+		.blocks = 1,
+		.ingress = true,
+	},
+	{
+		.vtype = VCAP_TYPE_IS2, /* IS2-0 */
+		.vinst = 0,
+		.map_id = 4,
+		.lookups = SPARX5_IS2_LOOKUPS,
+		.lookups_per_instance = SPARX5_IS2_LOOKUPS / 2,
+		.first_cid = SPARX5_VCAP_CID_IS2_L0,
+		.last_cid = SPARX5_VCAP_CID_IS2_L2 - 1,
+		.blockno = 0,
+		.blocks = 1,
+		.ingress = true,
+	},
+	{
+		.vtype = VCAP_TYPE_IS2, /* IS2-1 */
+		.vinst = 1,
+		.map_id = 5,
+		.lookups = SPARX5_IS2_LOOKUPS,
+		.lookups_per_instance = SPARX5_IS2_LOOKUPS / 2,
+		.first_cid = SPARX5_VCAP_CID_IS2_L2,
+		.last_cid = SPARX5_VCAP_CID_IS2_MAX,
+		.blockno = 1,
+		.blocks = 1,
+		.ingress = true,
+	},
+	{
+		.vtype = VCAP_TYPE_ES0,
+		.lookups = SPARX5_ES0_LOOKUPS,
+		.lookups_per_instance = SPARX5_ES0_LOOKUPS,
+		.first_cid = SPARX5_VCAP_CID_ES0_L0,
+		.last_cid = SPARX5_VCAP_CID_ES0_MAX,
+		.count = 1536,
+		.ingress = false,
+	},
+	{
+		.vtype = VCAP_TYPE_ES2,
+		.lookups = SPARX5_ES2_LOOKUPS,
+		.lookups_per_instance = SPARX5_ES2_LOOKUPS,
+		.first_cid = SPARX5_VCAP_CID_ES2_L0,
+		.last_cid = SPARX5_VCAP_CID_ES2_MAX,
+		.count = 1024,
+		.ingress = false,
+	},
+};
